Re: [PATCH 2/2] pci: Add PCIe driver for Rockchip Soc

[Wenrui Li <wenrui.li@rock-chips.com>]

Hi,

On 2016/5/27 15:13, Bharat Kumar Gogada wrote:
>>>
>>>> +
>>>> +static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
>>>> +				       struct pci_bus *bus, u32 devfn,
>>>> +				       int where, int size, u32 *val)
>>>> +{
>>>> +	u32 busdev;
>>>> +
>>>> +	busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
>>>> +				PCI_FUNC(devfn), where);
>>>> +
>>>> +	if (busdev & (size - 1)) {
>>>> +		*val = 0;
>>>> +		return PCIBIOS_BAD_REGISTER_NUMBER;
>>>> +	}
>>>> +
>>>> +	if (size == 4) {
>>>> +		*val = readl(pp->reg_base + busdev);
>>>> +	} else if (size == 2) {
>>>> +		*val = readw(pp->reg_base + busdev);
>>>> +	} else if (size == 1) {
>>>> +		*val = readb(pp->reg_base + busdev);
>>>> +	} else {
>>>> +		*val = 0;
>>>> +		return PCIBIOS_BAD_REGISTER_NUMBER;
>>>> +	}
>>>> +	return PCIBIOS_SUCCESSFUL;
>>>> +}
>>>> +
>>>
>>> This looks like the normal ECAM operations, you could just call those.
>>
>> I read ECAM reference code, I found it not support ioremap config space
>> for each bus individually on 64-bit systems. Our soc is 64-bit system,
>> and bus0 config space base address is 0xfda00000, bus1 base address is
>> 0xf8100000. So I think it is not normal ECAM operations, I do not know
>> if I have understood correctly?
>>
> Hi,
>
> I think Arnd was suggesting to use generic config read/write calls, pci_generic_config_read/pci_generic_config_write
> which does above functionality.

Yeah, I seem the pci_generic_config_write use writew/writeb for byte and 
word write. but our SOC not support byte and word write in RC config 
spcace. So I redefine the the pci_ops.write

>
> Bharat
>
>
>