From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754290AbcEaNwR (ORCPT ); Tue, 31 May 2016 09:52:17 -0400 Received: from regular1.263xmail.com ([211.150.99.134]:56109 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754099AbcEaNwQ (ORCPT ); Tue, 31 May 2016 09:52:16 -0400 X-Greylist: delayed 367 seconds by postgrey-1.27 at vger.kernel.org; Tue, 31 May 2016 09:52:14 EDT X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: huangtao@rock-chips.com X-FST-TO: huangtao@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: huangtao@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 4/5] clocksource: rockchip: add support for rk3399 SoC To: Daniel Lezcano , Caesar Wang , Heiko Stuebner References: <1464169802-6033-1-git-send-email-wxt@rock-chips.com> <1464169802-6033-5-git-send-email-wxt@rock-chips.com> <574CCCB4.1030001@linaro.org> Cc: dianders@chromium.org, briannorris@google.com, smbarber@google.com, linux-rockchip@lists.infradead.org, Thomas Gleixner , cf@rock-chips.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: "Huang, Tao" Message-ID: <574D95AF.2020905@rock-chips.com> Date: Tue, 31 May 2016 21:46:23 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <574CCCB4.1030001@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Daniel: On 2016年05月31日 07:28, Daniel Lezcano wrote: > On 05/25/2016 11:50 AM, Caesar Wang wrote: >> From: Huang Tao >> >> The CONTROL register offset is different from old SoCs. >> For Linux driver, there are not functional changes at all. >> Let's call it v2. >> >> Signed-off-by: Huang Tao >> Cc: Daniel Lezcano >> Cc: Thomas Gleixner >> Cc: Heiko Stuebner >> Tested-by: Jianqun Xu >> Signed-off-by: Caesar Wang >> --- > > That's hackish. Yes:( I blamed our IC guy. > > Please consider something like: > > diff --git a/drivers/clocksource/rockchip_timer.c > b/drivers/clocksource/rockchip_timer.c > index b991b28..b6ba6f9 100644 > --- a/drivers/clocksource/rockchip_timer.c > +++ b/drivers/clocksource/rockchip_timer.c > @@ -19,7 +19,8 @@ > > #define TIMER_LOAD_COUNT0 0x00 > #define TIMER_LOAD_COUNT1 0x04 > -#define TIMER_CONTROL_REG 0x10 > +#define TIMER_CONTROL_REG3288 0x10 > +#define TIMER_CONTROL_REG3399 0x1C > #define TIMER_INT_STATUS 0x18 > > #define TIMER_DISABLE 0x0 > @@ -31,6 +32,7 @@ > struct bc_timer { > struct clock_event_device ce; > void __iomem *base; > + void __iomem *ctrl; > u32 freq; > }; > > @@ -46,15 +48,20 @@ static inline void __iomem *rk_base(struct > clock_event_device *ce) > return rk_timer(ce)->base; > } > > +static inline void __iomem *rk_ctrl(struct clock_event_device *ce) > +{ > + return rk_timer(ce)->ctrl; > +} > + > static inline void rk_timer_disable(struct clock_event_device *ce) > { > - writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); > + writel_relaxed(TIMER_DISABLE, rk_ctrl(ce)); > } > > static inline void rk_timer_enable(struct clock_event_device *ce, u32 > flags) > { > writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, > - rk_base(ce) + TIMER_CONTROL_REG); > + rk_ctrl(ce)); > } > > static void rk_timer_update_counter(unsigned long cycles, > @@ -179,4 +186,18 @@ out_unmap: > iounmap(bc_timer.base); > } > > -CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init); > +static void __init rk3288_timer_init(struct device_node *np) > +{ > + bc_timer.ctrl = TIMER_CONTROL_REG3288; > + rk_timer_init(np); > +} > + > +static void __init rk3399_timer_init(struct device_node *np) > +{ > + bc_timer.ctrl = TIMER_CONTROL_REG3399; > + rk_timer_init(np); > +} > + > + > +CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", > rk3288_timer_init); > +CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3399-timer", > rk3399_timer_init); > > I think you mean this patch otherwise compile will fail: @@ -19,7 +19,8 @@ #define TIMER_LOAD_COUNT0 0x00 #define TIMER_LOAD_COUNT1 0x04 -#define TIMER_CONTROL_REG 0x10 +#define TIMER_CONTROL_REG3288 0x10 +#define TIMER_CONTROL_REG3399 0x1C #define TIMER_INT_STATUS 0x18 #define TIMER_DISABLE 0x0 @@ -31,6 +32,7 @@ struct bc_timer { struct clock_event_device ce; void __iomem *base; + u32 ctrl; u32 freq; }; @@ -46,15 +48,20 @@ static inline void __iomem *rk_base(struct clock_event_device *ce) return rk_timer(ce)->base; } +static inline void __iomem *rk_ctrl(struct clock_event_device *ce) +{ + return rk_timer(ce)->base + rk_timer(ce)->ctrl; +} + static inline void rk_timer_disable(struct clock_event_device *ce) { - writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); + writel_relaxed(TIMER_DISABLE, rk_ctrl(ce)); } static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags) { writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, - rk_base(ce) + TIMER_CONTROL_REG); + rk_ctrl(ce)); } static void rk_timer_update_counter(unsigned long cycles, @@ -179,4 +186,19 @@ out_unmap: iounmap(bc_timer.base); } -CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init); +static void __init rk3288_timer_init(struct device_node *np) +{ + bc_timer.ctrl = TIMER_CONTROL_REG3288; + rk_timer_init(np); +} + +static void __init rk3399_timer_init(struct device_node *np) +{ + bc_timer.ctrl = TIMER_CONTROL_REG3399; + rk_timer_init(np); +} + +CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", + rk3288_timer_init); +CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", + rk3399_timer_init); This patch will give us a little lager text size. If we do disassemble, we can see additional LDR is called. I can accept this performance drop. So we will send new patches. BTW, the patch "clocksource: rockchip: remove unnecessary clear irq before request_irq" can drop if we use this patch. Thanks, Huang, Tao