From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753543AbcFGHfP (ORCPT ); Tue, 7 Jun 2016 03:35:15 -0400 Received: from mail-sn1nam02on0067.outbound.protection.outlook.com ([104.47.36.67]:48115 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752129AbcFGHfM (ORCPT ); Tue, 7 Jun 2016 03:35:12 -0400 X-Greylist: delayed 1164 seconds by postgrey-1.27 at vger.kernel.org; Tue, 07 Jun 2016 03:35:12 EDT Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=bestguesspass action=none header.from=xilinx.com; Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger To: Marc Zyngier , Daniel Lezcano , Thomas Gleixner , "Rob Herring" , Mark Rutland References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> CC: Dinh Nguyen , Carlo Caione , Kevin Hilman , Duc Dang , Florian Fainelli , Ray Jui , Scott Branden , Kukjin Kim , Krzysztof Kozlowski , "Jason Cooper" , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Masahiro Yamada , Michal Simek , =?UTF-8?Q?S=c3=b6ren_Brinkmann?= , "Tirumalesh Chalamarla" , Jan Glauber , "Hou Zhiqiang" , Wenbin Song , Yuan Yao , Liu Gang , Mingkai Hu , Rajesh Bhagat , , , , , From: Michal Simek Message-ID: <5756757C.8040000@xilinx.com> Date: Tue, 7 Jun 2016 09:19:24 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22376.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(3190300001)(189002)(199003)(24454002)(575784001)(86362001)(6806005)(87936001)(92566002)(59896002)(5008740100001)(77096005)(65956001)(65806001)(4001350100001)(83506001)(8666004)(5001770100001)(8936002)(47776003)(50466002)(99136001)(106466001)(80316001)(9786002)(64126003)(81156014)(36386004)(50986999)(65816999)(76176999)(54356999)(87266999)(2950100001)(23746002)(36756003)(2906002)(230700001)(189998001)(4326007)(8676002)(19580405001)(19580395003)(586003)(81166006)(33656002)(63266004)(7059030)(107986001)(5001870100001);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2NAM02HT094;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;MX:1;A:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: 63cd4968-df2b-437b-90c3-08d38ea41b16 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:BL2NAM02HT094; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(180628864354917)(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(13017025)(8121501046)(13023025)(13015025)(13024025)(13018025)(10201501046)(3002001)(6055026);SRVR:BL2NAM02HT094;BCL:0;PCL:0;RULEID:;SRVR:BL2NAM02HT094; X-Forefront-PRVS: 09669DB681 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2016 07:19:46.4772 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT094 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6.6.2016 19:56, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- > arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- > arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- > arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- > arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- > 10 files changed, 40 insertions(+), 40 deletions(-) > > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > index 445aa67..c2b9bcb 100644 > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > @@ -255,10 +255,10 @@ > /* Local timer */ > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > timer0: timer0@ffc03000 { > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > index 832815d..4d9d144 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > @@ -100,13 +100,13 @@ > timer { > compatible = "arm,armv8-timer"; > interrupts = - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>; > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; > }; > > xtal: xtal-clk { > diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi > index 5147d76..1c4193f 100644 > --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi > +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi > @@ -110,10 +110,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ > - <1 13 0xff01>, /* Non-secure Phys IRQ */ > - <1 14 0xff01>, /* Virt IRQ */ > - <1 15 0xff01>; /* Hyp IRQ */ > + interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ > + <1 13 0xff08>, /* Non-secure Phys IRQ */ > + <1 14 0xff08>, /* Virt IRQ */ > + <1 15 0xff08>; /* Hyp IRQ */ > clock-frequency = <50000000>; > }; > > diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi > index ec68ec1..9c2d8a7 100644 > --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi > +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi > @@ -88,13 +88,13 @@ > timer { > compatible = "arm,armv8-timer"; > interrupts = - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > - IRQ_TYPE_EDGE_RISING)>; > + IRQ_TYPE_LEVEL_LOW)>; > }; > > pmu { > diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > index 2eb9b22..382d86f 100644 > --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > @@ -354,10 +354,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xff01>, > - <1 14 0xff01>, > - <1 11 0xff01>, > - <1 10 0xff01>; > + interrupts = <1 13 8>, > + <1 14 8>, > + <1 11 8>, > + <1 10 8>; > }; > > pmu { > diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi > index ca663df..1628315 100644 > --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi > @@ -473,10 +473,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xff01>, > - <1 14 0xff01>, > - <1 11 0xff01>, > - <1 10 0xff01>; > + interrupts = <1 13 0xff08>, > + <1 14 0xff08>, > + <1 11 0xff08>, > + <1 10 0xff08>; > }; > > pmu_system_controller: system-controller@105c0000 { > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > index c277ba6..b92543d 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > @@ -111,10 +111,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0x1>, /* Physical Secure PPI */ > - <1 14 0x1>, /* Physical Non-Secure PPI */ > - <1 11 0x1>, /* Virtual PPI */ > - <1 10 0x1>; /* Hypervisor PPI */ > + interrupts = <1 13 0xf08>, /* Physical Secure PPI */ > + <1 14 0xf08>, /* Physical Non-Secure PPI */ > + <1 11 0xf08>, /* Virtual PPI */ > + <1 10 0xf08>; /* Hypervisor PPI */ > fsl,erratum-a008585; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > index 20d256b..b1d6bb8 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > @@ -122,10 +122,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = , > - , > - , > - ; > + interrupts = , > + , > + , > + ; > }; > > odmi: odmi@300000 { > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > index 9532880..5a8e0f4 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > @@ -127,10 +127,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > soc { > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index e595f22..3e2e51f 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -65,10 +65,10 @@ > timer { > compatible = "arm,armv8-timer"; > interrupt-parent = <&gic>; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > amba_apu { > Acked-by: Michal Simek # ZynqMP Thanks, Michal