From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
	id S1756837AbcFHPzW (ORCPT <rfc822;w@1wt.eu>);
	Wed, 8 Jun 2016 11:55:22 -0400
Received: from hqemgate16.nvidia.com ([216.228.121.65]:2959 "EHLO
	hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
	with ESMTP id S1755884AbcFHPzS (ORCPT
	<rfc822;linux-kernel@vger.kernel.org>);
	Wed, 8 Jun 2016 11:55:18 -0400
X-PGP-Universal: processed;
	by hqnvupgp07.nvidia.com on Wed, 08 Jun 2016 08:52:07 -0700
Message-ID: <57583CE0.70501@nvidia.com>
Date: Wed, 8 Jun 2016 21:12:24 +0530
From: Laxman Dewangan <ldewangan@nvidia.com>
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0
MIME-Version: 1.0
To: Lee Jones <lee.jones@linaro.org>
CC: <broonie@kernel.org>, <gregkh@linuxfoundation.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] mfd: max77620: Add pre/post irq handler before/after
 servicing interrupt
References: <1463757027-1398-1-git-send-email-ldewangan@nvidia.com> <1463757027-1398-2-git-send-email-ldewangan@nvidia.com> <20160608144136.GL14888@dell>
In-Reply-To: <20160608144136.GL14888@dell>
X-Originating-IP: [10.19.65.30]
X-ClientProxiedBy: BGMAIL102.nvidia.com (10.25.59.11) To bgmail102.nvidia.com
 (10.25.59.11)
Content-Type: text/plain; charset="UTF-8"; format=flowed
Content-Transfer-Encoding: 7bit
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Hi Lee,

On Wednesday 08 June 2016 08:11 PM, Lee Jones wrote:
> On Fri, 20 May 2016, Laxman Dewangan wrote:
>
>> + * MAX77620 and MAX20024 has the following steps of the interrupt handling
>> + * for TOP interrupts:
>> + * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.
>> + * 2. Read IRQTOP and service the interrupt.
>> + * 3. Once all interrupts has been checked and serviced, the interrupt service
>> + *    routine un-masks the hardware interrupt line by clearing GLBLM.
>> + */
>> +static int max77620_top_irq_chip_pre_irq_handler(void *irq_drv_data)
>> +{
>> +	struct max77620_chip *chip = irq_drv_data;
>> +	int ret;
>> +
>> +	ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
>> +				 MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);
>> +	if (ret < 0)
>> +		dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
>> +
>> +	return ret;
>> +}
>> +
>> +static int max77620_top_irq_chip_post_irq_handler(void *irq_drv_data)
>> +{
>> +	struct max77620_chip *chip = irq_drv_data;
>> +	int ret;
>> +
>> +	ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
>> +				 MAX77620_GLBLM_MASK, 0);
>> +	if (ret < 0)
>> +		dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
>> +
>> +	return ret;
>> +}
> This seems massively over compacted.  All you're effectively doing
> here is masking and unmasking the IRQs, which we do almost
> ubiquitously with interrupt controllers.  Can't you just call the
> functions "max77629_{un}mask_irqs()"?
>
>

Actually, per PMIC HW design, we need to toggle this bit on ISRs. Before 
reading the status, need to set 1 and then after handling it need to set 
0. This cannot be done by any other bit toggling or masking/unmasking 
interrupt controller interrupt.

This is hard requirement from the PMIC chip.