From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752727AbcFIVGK (ORCPT ); Thu, 9 Jun 2016 17:06:10 -0400 Received: from mail-pa0-f66.google.com ([209.85.220.66]:36350 "EHLO mail-pa0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752212AbcFIVGG (ORCPT ); Thu, 9 Jun 2016 17:06:06 -0400 Message-ID: <5759DA3A.4070905@gmail.com> Date: Thu, 09 Jun 2016 14:06:02 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: David Daney CC: Marc Zyngier , Mark Rutland , Andrew Lunn , Krzysztof Kozlowski , Hou Zhiqiang , Liu Gang , Masahiro Yamada , Mingkai Hu , Florian Fainelli , Kevin Hilman , Daniel Lezcano , Michal Simek , linux-samsung-soc@vger.kernel.org, Kukjin Kim , bcm-kernel-feedback-list@broadcom.com, =?ISO-8859-1?Q?S=F6ren_Brinkman?= =?ISO-8859-1?Q?n?= , Sebastian Hesselbarth , Jason Cooper , Ray Jui , Tirumalesh Chalamarla , Rob Herring , Yuan Yao , Wenbin Song , Jan Glauber , Gregory Clement , linux-amlogic@lists.infradead.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Rajesh Bhagat , Scott Branden , Duc Dang , linux-kernel@vger.kernel.org, Carlo Caione , Dinh Nguyen Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> <5759B143.9070503@caviumnetworks.com> In-Reply-To: <5759B143.9070503@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org I spoke too soon... On 06/09/2016 11:11 AM, David Daney wrote: > On 06/06/2016 10:56 AM, Marc Zyngier wrote: >> The ARM architected timer specification mandates that the interrupt >> associated with each timer is level triggered (which corresponds to >> the "counter >= comparator" condition). >> >> A number of DTs are being remarkably creative, declaring the interrupt >> to be edge triggered. A quick look at the TRM for the corresponding ARM >> CPUs clearly shows that this is wrong, and I've corrected those. >> For non-ARM designs (and in the absence of a publicly available TRM), >> I've made them active low as well, which can't be completely wrong >> as the GIC cannot disinguish between level low and level high. >> >> The respective maintainers are of course welcome to prove me wrong. >> >> While I was at it, I took the liberty to fix a couple of related issue, >> such as some spurious affinity bits on ThunderX, and their complete >> absence on ls1043a (both of which seem to be related to copy-pasting >> from other DTs). >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >> 10 files changed, 40 insertions(+), 40 deletions(-) >> > [...] >> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >> index 2eb9b22..382d86f 100644 >> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >> @@ -354,10 +354,10 @@ >> >> timer { >> compatible = "arm,armv8-timer"; >> - interrupts = <1 13 0xff01>, >> - <1 14 0xff01>, >> - <1 11 0xff01>, >> - <1 10 0xff01>; >> + interrupts = <1 13 8>, >> + <1 14 8>, >> + <1 11 8>, >> + <1 10 8>; NAK! According to arm,gic-v3.txt the trigger value must be either 1 or 4: The 3rd cell is the flags, encoded as follows: bits[3:0] trigger type and level flags. 1 = edge triggered 4 = level triggered >> }; >> >> pmu { > > Acked-by: David Daney > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel