[PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE

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* [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and
@ 2016-06-10  4:56 Chanwoo Choi
  2016-06-10  4:56 ` [PATCH 1/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD Uart Chanwoo Choi
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Chanwoo Choi @ 2016-06-10  4:56 UTC (permalink / raw)
  To: s.nawrocki, tomasz.figa
  Cc: mturquette, sboyd, kgene, k.kozlowski, jh80.chung, jonghwa3.lee,
	beomho.seo, linux-samsung-soc, linux-clk, linux-arm-kernel,
	linux-kernel, Chanwoo Choi

This patch-set add the CLK_IGNORE_UNUSED flag to the specific clocks because
the specific clocks should remain the enable state. This patch-set support the
PCIE (PCI Express), serial3(AUD Uart) device and fix the hang issue for
suspend-to-ram.

Beomho Seo (1):
  clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD Uart

Jaehoon Chung (1):
  clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device

Jonghwa Lee (1):
  clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks occurring hang at sleep

 drivers/clk/samsung/clk-exynos5433.c   | 47 +++++++++++++++++++++-------------
 include/dt-bindings/clock/exynos5433.h |  3 ++-
 2 files changed, 31 insertions(+), 19 deletions(-)

-- 
1.9.1

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD Uart
  2016-06-10  4:56 [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and Chanwoo Choi
@ 2016-06-10  4:56 ` Chanwoo Choi
  2016-06-10  4:56 ` [PATCH 2/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks occurring hang at sleep Chanwoo Choi
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Chanwoo Choi @ 2016-06-10  4:56 UTC (permalink / raw)
  To: s.nawrocki, tomasz.figa
  Cc: mturquette, sboyd, kgene, k.kozlowski, jh80.chung, jonghwa3.lee,
	beomho.seo, linux-samsung-soc, linux-clk, linux-arm-kernel,
	linux-kernel, Chanwoo Choi

From: Beomho Seo <beomho.seo@samsung.com>

This patch adds the CLK_IGNORE_UNUSED flag for sclk_aud_uart gate clock
for uart3 opeation.

Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/clk/samsung/clk-exynos5433.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 128527b8fbeb..e1a9c24079a4 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2976,7 +2976,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
 	GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
 			ENABLE_SCLK_AUD1, 4, 0, 0),
 	GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
-			ENABLE_SCLK_AUD1, 3, 0, 0),
+			ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
 			ENABLE_SCLK_AUD1, 2, 0, 0),
 	GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 2/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks occurring hang at sleep
  2016-06-10  4:56 [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and Chanwoo Choi
  2016-06-10  4:56 ` [PATCH 1/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD Uart Chanwoo Choi
@ 2016-06-10  4:56 ` Chanwoo Choi
  2016-06-10  4:56 ` [PATCH 3/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device Chanwoo Choi
  2016-06-10 10:29 ` [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and Sylwester Nawrocki
  3 siblings, 0 replies; 5+ messages in thread
From: Chanwoo Choi @ 2016-06-10  4:56 UTC (permalink / raw)
  To: s.nawrocki, tomasz.figa
  Cc: mturquette, sboyd, kgene, k.kozlowski, jh80.chung, jonghwa3.lee,
	beomho.seo, linux-samsung-soc, linux-clk, linux-arm-kernel,
	linux-kernel, Chanwoo Choi

From: Jonghwa Lee <jonghwa3.lee@samsung.com>

Some clocks are required being unmasked during suspend-to-ram. Otherwise,
PMU will stuck and power line never down.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/clk/samsung/clk-exynos5433.c | 34 ++++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index e1a9c24079a4..852ac6a7607e 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -668,11 +668,14 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
 	GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
 			ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
-			ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
+			ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
+			CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
-			ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
+			ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
+			CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
-			ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
+			ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
+			CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
 			ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
@@ -833,7 +836,7 @@ static struct samsung_div_clock cpif_div_clks[] __initdata = {
 static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
 	/* ENABLE_SCLK_CPIF */
 	GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
-			ENABLE_SCLK_CPIF, 9, 0, 0),
+			ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
 			ENABLE_SCLK_CPIF, 4, 0, 0),
 };
@@ -1440,11 +1443,13 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = {
 
 	/* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
 	GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
-			ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
+			ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
+			CLK_IGNORE_UNUSED, 0),
 
 	/* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
 	GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
-			ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
+			ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
+			CLK_IGNORE_UNUSED, 0),
 
 	/* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
 	GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
@@ -1674,11 +1679,14 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
 	GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
 			3, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
-			ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+			ENABLE_SCLK_PERIC, 2,
+			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
-			ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+			ENABLE_SCLK_PERIC, 1,
+			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
-			ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+			ENABLE_SCLK_PERIC, 0,
+			CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 };
 
 static struct samsung_cmu_info peric_cmu_info __initdata = {
@@ -2962,7 +2970,7 @@ static struct samsung_gate_clock aud_gate_clks[] __initdata = {
 
 	/* ENABLE_SCLK_AUD0 */
 	GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
-			2, 0, 0),
+			2, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
 			ENABLE_SCLK_AUD0, 1, 0, 0),
 	GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
@@ -3356,9 +3364,11 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
 	GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
 			ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
-			"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
+			"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
+			CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
-			"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
+			"mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
+			CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
 			ENABLE_ACLK_GSCL, 3, 0, 0),
 	GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 3/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device
  2016-06-10  4:56 [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and Chanwoo Choi
  2016-06-10  4:56 ` [PATCH 1/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD Uart Chanwoo Choi
  2016-06-10  4:56 ` [PATCH 2/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks occurring hang at sleep Chanwoo Choi
@ 2016-06-10  4:56 ` Chanwoo Choi
  2016-06-10 10:29 ` [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and Sylwester Nawrocki
  3 siblings, 0 replies; 5+ messages in thread
From: Chanwoo Choi @ 2016-06-10  4:56 UTC (permalink / raw)
  To: s.nawrocki, tomasz.figa
  Cc: mturquette, sboyd, kgene, k.kozlowski, jh80.chung, jonghwa3.lee,
	beomho.seo, linux-samsung-soc, linux-clk, linux-arm-kernel,
	linux-kernel, Chanwoo Choi

From: Jaehoon Chung <jh80.chung@samsung.com>

This patch adds the CLK_IGNORE_UNUSED flag for PCI Express's clocks
which need the on state and the 'pcie' gate clock.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
 drivers/clk/samsung/clk-exynos5433.c   | 11 ++++++-----
 include/dt-bindings/clock/exynos5433.h |  3 ++-
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 852ac6a7607e..e3cc9359fb20 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -639,7 +639,7 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
 
 	/* ENABLE_SCLK_TOP_FSYS */
 	GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
-			ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
+			ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
 			ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
@@ -2146,7 +2146,7 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
 	GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
 			ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
-			ENABLE_ACLK_FSYS1, 24, 0, 0),
+			ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
 			"mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
 			22, CLK_IGNORE_UNUSED, 0),
@@ -2193,13 +2193,13 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
 
 	/* ENABLE_PCLK_FSYS */
 	GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
-			ENABLE_PCLK_FSYS, 17, 0, 0),
+			ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
 			ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
-			ENABLE_PCLK_FSYS, 14, 0, 0),
+			ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
-			ENABLE_PCLK_FSYS, 13, 0, 0),
+			ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
 			ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
 	GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
@@ -2278,6 +2278,7 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
 			ENABLE_SCLK_FSYS, 0, 0, 0),
 
 	/* ENABLE_IP_FSYS0 */
+	GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
 	GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
 	GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
 };
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 8e024fea26e7..4fa6bb2136e3 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -622,8 +622,9 @@
 #define CLK_SCLK_UFSUNIPRO		112
 #define CLK_SCLK_USBHOST30		113
 #define CLK_SCLK_USBDRD30		114
+#define CLK_PCIE			115
 
-#define FSYS_NR_CLK			115
+#define FSYS_NR_CLK			116
 
 /* CMU_G2D */
 #define CLK_MUX_ACLK_G2D_266_USER	1
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and
  2016-06-10  4:56 [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and Chanwoo Choi
                   ` (2 preceding siblings ...)
  2016-06-10  4:56 ` [PATCH 3/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device Chanwoo Choi
@ 2016-06-10 10:29 ` Sylwester Nawrocki
  3 siblings, 0 replies; 5+ messages in thread
From: Sylwester Nawrocki @ 2016-06-10 10:29 UTC (permalink / raw)
  To: Chanwoo Choi
  Cc: tomasz.figa, mturquette, sboyd, kgene, k.kozlowski, jh80.chung,
	jonghwa3.lee, beomho.seo, linux-samsung-soc, linux-clk,
	linux-arm-kernel, linux-kernel

On 06/10/2016 06:56 AM, Chanwoo Choi wrote:
> This patch-set add the CLK_IGNORE_UNUSED flag to the specific clocks because
> the specific clocks should remain the enable state. This patch-set support the
> PCIE (PCI Express), serial3(AUD Uart) device and fix the hang issue for
> suspend-to-ram.
> 
> Beomho Seo (1):
>   clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD Uart
> 
> Jaehoon Chung (1):
>   clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device
> 
> Jonghwa Lee (1):
>   clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks occurring hang at sleep

I applied these patches, after slightly editing the descriptions.
I also tested with the audio subsystem patches on top of 4.7-rc1 tree
and with AUD UART enabled. Everything seems to be working fine, there
was no any "external abort" exceptions.

-- 
Thanks,
Sylwester

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2016-06-10 10:29 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2016-06-10  4:56 [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and Chanwoo Choi
2016-06-10  4:56 ` [PATCH 1/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD Uart Chanwoo Choi
2016-06-10  4:56 ` [PATCH 2/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks occurring hang at sleep Chanwoo Choi
2016-06-10  4:56 ` [PATCH 3/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device Chanwoo Choi
2016-06-10 10:29 ` [PATCH 0/3] clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag and Sylwester Nawrocki

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