From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1424899AbcFMPuR (ORCPT ); Mon, 13 Jun 2016 11:50:17 -0400 Received: from smtp2-g21.free.fr ([212.27.42.2]:17787 "EHLO smtp2-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1424531AbcFMPuN (ORCPT ); Mon, 13 Jun 2016 11:50:13 -0400 Subject: Re: Using irq-crossbar.c To: Lennart Sorensen , Sebastian Frias Cc: Marc Zyngier , Thomas Gleixner , LKML , Grygorii Strashko , Mans Rullgard References: <575ADEBA.2030202@laposte.net> <575AE52E.9020005@arm.com> <575B16BD.50600@free.fr> <20160611105840.69324f8e@arm.com> <575C304F.2070303@free.fr> <20160613140405.GB5829@csclub.uwaterloo.ca> <575EC9C9.3040201@laposte.net> <20160613154223.GP5827@csclub.uwaterloo.ca> From: Mason Message-ID: <575ED623.1070902@free.fr> Date: Mon, 13 Jun 2016 17:49:55 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:43.0) Gecko/20100101 Firefox/43.0 SeaMonkey/2.40 MIME-Version: 1.0 In-Reply-To: <20160613154223.GP5827@csclub.uwaterloo.ca> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/06/2016 17:42, Lennart Sorensen wrote: > On Mon, Jun 13, 2016 at 04:57:13PM +0200, Sebastian Frias wrote: >> Actually we have 128 inputs and 24 outputs, the 24 outputs go straight to the GIC. >> The HW block is a many-to-many router. >> There are 128 32bit registers which specify, for each of the corresponding 128 inputs, to which of the 24 outputs it would be routed to. >> >> There are 4 32bit registers that can show the RAW status of the 128 inputs, but they do not latch on the inputs. >> That's why our understanding is that on Linux terms it is not an interrupt controller, but just a many-to-many mux, the only real interrupt-controller (where one can set if the line is active high or low for example) is the GIC. > > Well that does just sound like a mux. But that does mean you either > can't use more than 24 inputs at once, or you will be sharing interrupts. > > I really hate shared interrupts so I would never design something that > way, but it is simpler. If I am not mistaken, the Cortex A9 MPCore GIC has 32 inputs. So any SoC with more than 32 devices capable of generating IRQs would have to share interrupts, right? Regards.