From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933330AbcFOPgY (ORCPT ); Wed, 15 Jun 2016 11:36:24 -0400 Received: from foss.arm.com ([217.140.101.70]:38383 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932432AbcFOPgW (ORCPT ); Wed, 15 Jun 2016 11:36:22 -0400 Subject: Re: [PATCH] ARM: V7M: Add dsb before jumping in handler mode To: Alexandre TORGUE , Russell King , Ezequiel Garcia , u.kleine-koenig@pengutronix.de, Maxime Coquelin References: <1465827171-15847-1-git-send-email-alexandre.torgue@st.com> Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Vladimir Murzin Message-ID: <576175F3.5080306@arm.com> Date: Wed, 15 Jun 2016 16:36:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1465827171-15847-1-git-send-email-alexandre.torgue@st.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/06/16 15:12, Alexandre TORGUE wrote: > According to ARM AN321 (section 4.12): > > "If the vector table is in writable memory such as SRAM, either relocated > by VTOR or a device dependent memory remapping mechanism, then > architecturally a memory barrier instruction is required after the vector > table entry is updated, and if the exception is to be activated > immediately" > > Signed-off-by: Maxime Coquelin > Signed-off-by: Alexandre TORGUE > Reviewed-by: Vladimir Murzin > diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S > index 7229d8d..2ddc435 100644 > --- a/arch/arm/mm/proc-v7m.S > +++ b/arch/arm/mm/proc-v7m.S > @@ -104,6 +104,7 @@ __v7m_setup: > badr r1, 1f > ldr r5, [r12, #11 * 4] @ read the SVC vector entry > str r1, [r12, #11 * 4] @ write the temporary SVC vector entry > + dsb > mov r6, lr @ save LR > ldr sp, =init_thread_union + THREAD_START_SP > cpsie i >