From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754626AbcFPN3g (ORCPT ); Thu, 16 Jun 2016 09:29:36 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13280 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754240AbcFPN3d (ORCPT ); Thu, 16 Jun 2016 09:29:33 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 16 Jun 2016 06:26:48 -0700 Message-ID: <5762A6A4.6030604@nvidia.com> Date: Thu, 16 Jun 2016 18:46:20 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Jon Hunter , , , CC: , , , Subject: Re: [PATCH V7 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage References: <1463755530-20941-1-git-send-email-ldewangan@nvidia.com> <1463755530-20941-4-git-send-email-ldewangan@nvidia.com> <5742C773.6080609@nvidia.com> <57443193.5010900@nvidia.com> In-Reply-To: <57443193.5010900@nvidia.com> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Thierry, On Tuesday 24 May 2016 04:18 PM, Jon Hunter wrote: > On 23/05/16 10:03, Jon Hunter wrote: >> On 20/05/16 15:45, Laxman Dewangan wrote: >>> The IO pins of Tegra SoCs are grouped for common control of IO >>> interface like setting voltage signal levels and power state of >>> the interface. The group is generally referred as IO pads. The >>> power state and voltage control of IO pins can be done at IO pads >>> level. >>> >>> Tegra generation SoC supports the power down of IO pads when it >>> is not used even in the active state of system. This saves power >>> from that IO interface. Also it supports multiple voltage level >>> in IO pins for interfacing on some of pads. The IO pad voltage is >>> automatically detected till T124, hence SW need not to configure >>> this. But from T210, the automatically detection logic has been >>> removed, hence SW need to explicitly set the IO pad voltage into >>> IO pad configuration registers. >>> >>> Add support to set the power states and voltage level of the IO pads >>> from client driver. The implementation for the APIs are in generic >>> which is applicable for all generation os Tegra SoC. >>> >>> IO pads ID and information of bit field for power state and voltage >>> level controls are added for Tegra124, Tegra132 and Tegra210. The SOR >>> driver is modified to use the new APIs. >>> >>> Signed-off-by: Laxman Dewangan Can you please review this? Thanks, Laxman