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X-CSE-ConnectionGUID: Sgsw640MT620RsRGMbOOkQ== X-CSE-MsgGUID: qHS9RrHyStSa7RP+lN0E9g== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="10155829" X-IronPort-AV: E=Sophos;i="6.07,245,1708416000"; d="scan'208";a="10155829" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 May 2024 03:01:29 -0700 X-CSE-ConnectionGUID: udJhc1hNT0e0Cs8MdxtM1Q== X-CSE-MsgGUID: Hg8wu7WfTWWT6SwKQNXnkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,245,1708416000"; d="scan'208";a="27230625" Received: from blu2-mobl.ccr.corp.intel.com (HELO [10.124.225.176]) ([10.124.225.176]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 May 2024 03:01:25 -0700 Message-ID: <57678928-4557-4975-ae23-7e11904e5302@linux.intel.com> Date: Wed, 1 May 2024 18:01:22 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: baolu.lu@linux.intel.com, Palmer Dabbelt , Albert Ou , Anup Patel , Sunil V L , Nick Kossifidis , Sebastien Boeuf , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com Subject: Re: [PATCH v3 3/7] iommu/riscv: Add RISC-V IOMMU PCIe device driver To: Tomasz Jeznach , Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley References: <3a04bd180fd510cb90e8d8dba5fb60f207e5e83f.1714494653.git.tjeznach@rivosinc.com> Content-Language: en-US From: Baolu Lu In-Reply-To: <3a04bd180fd510cb90e8d8dba5fb60f207e5e83f.1714494653.git.tjeznach@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2024/5/1 4:01, Tomasz Jeznach wrote: > Introduce device driver for PCIe implementation > of RISC-V IOMMU architected hardware. > > IOMMU hardware and system support for MSI or MSI-X is > required by this implementation. > > Vendor and device identifiers used in this patch > matches QEMU implementation of the RISC-V IOMMU PCIe > device, from Rivos VID (0x1efd) range allocated by the PCI-SIG. > > MAINTAINERS | added iommu-pci.c already covered by matching pattern. > > Link:https://lore.kernel.org/qemu-devel/20240307160319.675044-1-dbarboza@ventanamicro.com/ > Co-developed-by: Nick Kossifidis > Signed-off-by: Nick Kossifidis > Signed-off-by: Tomasz Jeznach > --- > drivers/iommu/riscv/Kconfig | 5 ++ > drivers/iommu/riscv/Makefile | 1 + > drivers/iommu/riscv/iommu-pci.c | 119 ++++++++++++++++++++++++++++++++ > 3 files changed, 125 insertions(+) > create mode 100644 drivers/iommu/riscv/iommu-pci.c Reviewed-by: Lu Baolu Best regards, baolu