From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751700AbcFVJTb (ORCPT ); Wed, 22 Jun 2016 05:19:31 -0400 Received: from foss.arm.com ([217.140.101.70]:45978 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750904AbcFVJT2 (ORCPT ); Wed, 22 Jun 2016 05:19:28 -0400 Subject: Re: [PATCH] coresight: document binding acronyms To: Mathieu Poirier , robh+dt@kernel.org, mark.rutland@arm.com References: <1466534486-22422-1-git-send-email-mathieu.poirier@linaro.org> Cc: Sudeep Holla , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, olof@lixom.net From: Sudeep Holla Organization: ARM Message-ID: <576A57DA.8090309@arm.com> Date: Wed, 22 Jun 2016 10:18:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1466534486-22422-1-git-send-email-mathieu.poirier@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/06/16 19:41, Mathieu Poirier wrote: > It can be hard for people not familiar with the CoreSight IP blocks > to make sense of the acronyms found in the current bindings. As such > this patch expands each acronym in the hope of providing a better > description of the IP block they represent. > Thanks for adding these info so quickly. Just a minor nit below. > Signed-off-by: Mathieu Poirier > --- > .../devicetree/bindings/arm/coresight.txt | 32 ++++++++++++++++------ > 1 file changed, 24 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index 93147c0c8a0e..c73a7f773998 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -12,14 +12,30 @@ its hardware characteristcs. > > * compatible: These have to be supplemented with "arm,primecell" as > drivers are using the AMBA bus interface. Possible values include: > - - "arm,coresight-etb10", "arm,primecell"; > - - "arm,coresight-tpiu", "arm,primecell"; > - - "arm,coresight-tmc", "arm,primecell"; > - - "arm,coresight-funnel", "arm,primecell"; > - - "arm,coresight-etm3x", "arm,primecell"; > - - "arm,coresight-etm4x", "arm,primecell"; > - - "qcom,coresight-replicator1x", "arm,primecell"; > - - "arm,coresight-stm", "arm,primecell"; [1] > + - Embedded Trace Buffer (version 1.0): > + "arm,coresight-etb10", "arm,primecell"; > + > + - Trace Port Interface Unit: > + "arm,coresight-tpiu", "arm,primecell"; > + > + - Trace Memory Controller (ETB, ETF, ETR): Only ETB is expanded in the list, does it make sense to expand ETF and ETR too ? -- Regards, Sudeep