From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751996AbcFVKxc (ORCPT ); Wed, 22 Jun 2016 06:53:32 -0400 Received: from foss.arm.com ([217.140.101.70]:46685 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751262AbcFVKx3 (ORCPT ); Wed, 22 Jun 2016 06:53:29 -0400 Subject: Re: [PATCH] coresight: etm4x: request to retain power to the trace unit when active To: Sudeep Holla , Mathieu Poirier References: <1466590513-22505-1-git-send-email-sudeep.holla@arm.com> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org From: Suzuki K Poulose Message-ID: <576A6C84.4090304@arm.com> Date: Wed, 22 Jun 2016 11:46:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1466590513-22505-1-git-send-email-sudeep.holla@arm.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/06/16 11:15, Sudeep Holla wrote: > The Coresight ETMv4 architecture provides a way to request to keep the > power to the trace unit. This might help to collect the traces without > the need to disable the CPU power management(entering/exiting deeper > idle states). > > Trace PowerDown Control Register provides powerup request bit which when > set requests the system to retain power to the trace unit and emulate > the powerdown request. > > Typically, a trace unit drives a signal to the power controller to > request that the trace unit core power domain is powered up. However, > if the trace unit and the CPU are in the same power domain then the > implementation might combine the trace unit power up status with a > signal from the CPU. > > This patch requests to retain power to the trace unit when active and > to remove when inactive. Note this change will only request but the > behaviour depends on the implementation. However, it matches the > exact behaviour expected when the external debugger is connected with > respect to CPU power states. > > Cc: Mathieu Poirier > Signed-off-by: Sudeep Holla Thanks for debugging this issue patiently and fixing it :) One comment below. > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index d6f1d6d874eb..301ee3232f3d 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -163,6 +163,12 @@ static void etm4_enable_hw(void *info) > writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); > writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); > > + /* > + * Request to keep the trace unit powered and also > + * emulation of powerdown > + */ > + writel_relaxed(TRCPDCR_PU, drvdata->base + TRCPDCR); > + > > @@ -293,6 +299,9 @@ static void etm4_disable_hw(void *info) > > + /* power can be removed from the trace unit now */ > + writel_relaxed(0, drvdata->base + TRCPDCR); > + At the moment the other bits in TRCPDCR are reserved (RES0). However to prevent issues in the future, it would be safer to read the value and set/clear the Bit of our interest than blindly writing those values. Suzuki