From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752744AbcFVMiy (ORCPT ); Wed, 22 Jun 2016 08:38:54 -0400 Received: from mga04.intel.com ([192.55.52.120]:54888 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752686AbcFVMit (ORCPT ); Wed, 22 Jun 2016 08:38:49 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,509,1459839600"; d="scan'208";a="833125750" Subject: Re: [PATCH v3 06/15] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes To: Douglas Anderson , ulf.hansson@linaro.org, Heiko Stuebner References: <1466445414-11974-1-git-send-email-dianders@chromium.org> <1466445414-11974-7-git-send-email-dianders@chromium.org> Cc: kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, groeck@chromium.org, michal.simek@xilinx.com, soren.brinkmann@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: <576A85C5.2060700@intel.com> Date: Wed, 22 Jun 2016 15:34:13 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <1466445414-11974-7-git-send-email-dianders@chromium.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/06/16 20:56, Douglas Anderson wrote: > In commit 802ac39a5566 ("mmc: sdhci-of-arasan: fix set_clock when a phy > is supported") we added code to power the PHY off and on whenever the > clock was changed but we avoided doing the power cycle code when the > clock was low speed. Let's now do it always. > > Although there may be other reasons for power cycling the PHY when the > clock changes, one of the main reasons is that we need to give the DLL a > chance to re-lock with the new clock. > > One of the things that the DLL is for is tuning the Receive Clock in > HS200 mode and STRB in HS400 mode. Thus it is clear that we should make > sure we power cycle the PHY (and wait for the DLL to lock) when we know > we'll be in one of these two speed modes. That's what the original code > did, though it used the clock rate rather than the speed mode. However, > even in speed modes other than HS200,/HS400 the DLL is used for > something since it can be clearly observed that the PHY doesn't function > properly if you leave the DLL off. > > Although it appears less important to power cycle the PHY and wait for > the DLL to lock when not in HS200/HS400 modes (no bugs were reported), > it still seems wise to let the locking always happen nevertheless. > > Note: as part of this, we make sure that we never try to turn the PHY on > when the clock is off (when the clock rate is 0). The PHY cannot work > when the clock is off since its DLL can't lock. > > This change requires ("phy: rockchip-emmc: Increase lock time > allowance") and will cause problems if picked without that change. > > Signed-off-by: Douglas Anderson > Reviewed-by: Shawn Lin > Tested-by: Heiko Stuebner Acked-by: Adrian Hunter