From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752212AbcF1L5r (ORCPT ); Tue, 28 Jun 2016 07:57:47 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:25013 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752112AbcF1L4O (ORCPT ); Tue, 28 Jun 2016 07:56:14 -0400 Subject: Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec To: Russell King - ARM Linux References: <1467106837-20996-1-git-send-email-patrice.chotard@st.com> <20160628094914.GI1041@n2100.armlinux.org.uk> CC: , , , , From: Patrice Chotard Message-ID: <577265B8.5030009@st.com> Date: Tue, 28 Jun 2016 13:55:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <20160628094914.GI1041@n2100.armlinux.org.uk> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.1.66] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-06-28_08:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Russell On 06/28/2016 11:49 AM, Russell King - ARM Linux wrote: > On Tue, Jun 28, 2016 at 11:40:37AM +0200, patrice.chotard@st.com wrote: >> From: Patrice Chotard >> >> This patch implements the write_sec callback that handle PL310 >> secure registers writes. >> This callback is just a stub for now, to avoid system crash. >> Later, it could handle SMC calls so that TZ handles the needed writes. > Is there much point having the L2 cache DT node enabled if you have > no support for the writes, which are required for the hardware to be > enabled? > It's similar to what has been done for ux500 machine, in non secure mode, we can't write in L2 cache secure registers. Patrice