Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk[Involving remittance information, please pay attention to the safety of property]

[William Wu <william.wu@rock-chips.com>]

Dear Rob,

On 07/01/2016 10:38 AM, Rob Herring wrote:
> On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote:
>> Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
>> which specifies whether disable delay PHY power change
>> from P0 to P1/P2/P3 when link state changing from U0
>> to U1/U2/U3 respectively.
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>> Changes in v5:
>> - None
>>
>> Changes in v4:
>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - None
>>
>>   Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
>>   drivers/usb/dwc3/core.c                        | 5 +++++
>>   drivers/usb/dwc3/core.h                        | 3 +++
>>   3 files changed, 10 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
>> index 34d13a5..bd5bef0 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> @@ -42,6 +42,8 @@ Optional properties:
>>    - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
>>   			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
>>   			a free-running PHY clock.
>> + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
>> +			from P0 to P1/P2/P3 without delay.
> Use '-', not '_'.
OK, I'll fix it in next patch.
Thanks~:-)

Best regards,
         William Wu
>
>>    - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface.
>>    - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY
>>   			with an 8- or 16-bit interface. Value 0 select 8-bit
>
>
>