From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752858AbcGCRKr (ORCPT ); Sun, 3 Jul 2016 13:10:47 -0400 Received: from www.sr71.net ([198.145.64.142]:56503 "EHLO blackbird.sr71.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752720AbcGCRKq (ORCPT ); Sun, 3 Jul 2016 13:10:46 -0400 Subject: Re: [PATCH 6/6] x86: Fix stray A/D bit setting into non-present PTEs To: Brian Gerst , Linus Torvalds References: <20160701001209.7DA24D1C@viggo.jf.intel.com> <20160701001218.3D316260@viggo.jf.intel.com> Cc: Linux Kernel Mailing List , the arch/x86 maintainers , linux-mm , Andrew Morton , Borislav Petkov , Andi Kleen , Michal Hocko , Dave Hansen From: Dave Hansen Message-ID: <5779470F.8020205@sr71.net> Date: Sun, 3 Jul 2016 10:10:39 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/30/2016 08:06 PM, Brian Gerst wrote: >> > It's not like anybody will ever care about 32-bit page tables on >> > Knights Landing anyway. > Could this affect a 32-bit guest VM? This isn't about 32-bit *mode*. It's about using the the 32-bit 2-level _paging_ mode that supports only 4GB virtual and 4GB physical addresses. That mode also doesn't support the No-eXecute (NX) bit, which basically everyone needs today for its security benefits. Even the little Quark CPU supports PAE (64-bit page tables).