From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756184AbcGGGb1 (ORCPT ); Thu, 7 Jul 2016 02:31:27 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:36655 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751179AbcGGGbZ (ORCPT ); Thu, 7 Jul 2016 02:31:25 -0400 Subject: Re: [PATCH v2 2/2] clk: hi6220: initialize UART1 clock to 150MHz To: Michael Turquette , Guodong Xu , sboyd@codeaurora.org, xinliang.liu@linaro.org, john.stultz@linaro.org References: <1467189955-21694-1-git-send-email-guodong.xu@linaro.org> <1467189955-21694-2-git-send-email-guodong.xu@linaro.org> <146784139106.73491.6417383579004254897@resonance> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org From: Jorge Ramirez Message-ID: <577DF73A.1030701@linaro.org> Date: Thu, 7 Jul 2016 08:31:22 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <146784139106.73491.6417383579004254897@resonance> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/06/2016 11:43 PM, Michael Turquette wrote: > Quoting Guodong Xu (2016-06-29 01:45:55) >> >From: Jorge Ramirez-Ortiz >> > >> >Early at boot, during the sys_clk initialization, make sure UART1 uses >> >the higher frequency clock, 150MHz. >> > >> >This enables support for higher baud rates (up to 3Mbps) in UART1, which >> >is required by faster bluetooth transfers. >> > >> >v2: use clk_set_rate() to propergate clock settings. >> > >> >Signed-off-by: Jorge Ramirez-Ortiz >> >Signed-off-by: Guodong Xu >> >--- >> > drivers/clk/hisilicon/clk-hi6220.c | 4 ++++ >> > 1 file changed, 4 insertions(+) >> > >> >diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c >> >index a36ffcb..631c56f 100644 >> >--- a/drivers/clk/hisilicon/clk-hi6220.c >> >+++ b/drivers/clk/hisilicon/clk-hi6220.c >> >@@ -12,6 +12,7 @@ >> > >> > #include >> > #include >> >+#include >> > #include >> > #include >> > #include >> >@@ -192,6 +193,9 @@ static void __init hi6220_clk_sys_init(struct device_node *np) >> > >> > hi6220_clk_register_divider(hi6220_div_clks_sys, >> > ARRAY_SIZE(hi6220_div_clks_sys), clk_data); >> >+ >> >+ if (clk_set_rate(clk_data->clk_data.clks[HI6220_UART1_SRC], 150000000)) >> >+ pr_err("failed to set uart1 clock rate\n"); > Why doesn't the UART driver call clk_get and then clk_set_rate on this > clock? Why do it in the clk provider driver? yes that was my initial choice as well; in the end I opted to do it in the clock driver because of it being a value that will not have to ever change for the SoC and - maybe more importantly- because of not having a DT property available for the primecell pl011 uart where to specify the value (so I thought this was a less intrusive implementation).