From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753788AbcGGKqG (ORCPT ); Thu, 7 Jul 2016 06:46:06 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:30436 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750817AbcGGKqE (ORCPT ); Thu, 7 Jul 2016 06:46:04 -0400 X-AuditID: cbfec7f4-f796c6d000001486-a0-577e32e81a3e Subject: Re: [PATCH v3 1/2] clk: samsung: cpu: Prepare for addition for Exynos7 CPU clocks To: Abhilash Kesavan References: <1467750561-13957-1-git-send-email-a.kesavan@samsung.com> <1467750561-13957-2-git-send-email-a.kesavan@samsung.com> Cc: tomasz.figa@gmail.com, kgene.kim@samsung.com, k.kozlowski@samsung.com, b.zolnierkie@samsung.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org From: Sylwester Nawrocki Message-id: <577E32E5.4010902@samsung.com> Date: Thu, 07 Jul 2016 12:45:57 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-version: 1.0 In-reply-to: <1467750561-13957-2-git-send-email-a.kesavan@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrELMWRmVeSWpSXmKPExsVy+t/xa7ovjOrCDZZeZbN4vGYxk8XGGetZ LV6/MLToXQAU2vT4GqvFx557rBaXd81hs5hxfh+TxcVTrhY/znSzWKza9YfRgdvj/Y1Wdo/L fb1MHjtn3WX32Lyk3qNvyypGj8+b5ALYorhsUlJzMstSi/TtErgyXjT+Yi9YylEx58tUlgbG D2xdjJwcEgImEgtnTmCFsMUkLtxbDxTn4hASWMoosftNLzOE85xR4vTJzUwgVcICMRKb7s9i AbFFBHQkHs/pYYQoamSUuNH0FsxhFpjFJHHq00NGkCo2AUOJ3qN9YDavgJZE45+zzCA2i4Cq xMbLx9hBbFGBCIknc09C1QhK/Jh8D2wDp4CbxJ2PS4FsDqChehL3L2qBhJkF5CU2r3nLPIFR YBaSjlkIVbOQVC1gZF7FKJpamlxQnJSea6hXnJhbXJqXrpecn7uJERITX3YwLj5mdYhRgINR iYd3QU5tuBBrYllxZe4hRgkOZiUR3grDunAh3pTEyqrUovz4otKc1OJDjNIcLErivHN3vQ8R EkhPLEnNTk0tSC2CyTJxcEo1MK64F3tuzpM5r9q3+/g+DPhxKG61eHqVK3OCuHqjk/Q7Pnd1 /tn/P8wSmPRPQn/3LdWnSX7P8/INPoXty6jYbLnm1QvHKfP7/tR/XdCe95ch/tjJ7t6pYbpi UzoeHUyzr/0vlvHaJ9/Vv6LaNuNeqOs/53KPXMmeH6t+HXdgyHidaGW0bB3rXiWW4oxEQy3m ouJEABfGetuFAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/05/2016 10:29 PM, Abhilash Kesavan wrote: > Exynos7 has the same CPU clock registers layout as that present > in Exynos5433 except for the bits in the MUX_STAT* registers. > Add a new CLK_CPU_HAS_MODIFIED_MUX_STAT flag to handle this change. > --- a/drivers/clk/samsung/clk-cpu.h > +++ b/drivers/clk/samsung/clk-cpu.h > @@ -63,6 +63,8 @@ struct exynos_cpuclk { > /* The CPU clock registers have Exynos5433-compatible layout */ > #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) > +/* Exynos5433-compatible layout with different MUX_STAT register bits */ > +#define CLK_CPU_HAS_MODIFIED_MUX_STAT (1 << 3) It's getting a bit messy, what if there comes another SoC version which has some other modification of exynos5433 registers structure? We would need another variant of HAS_MODIFIED_MUX_STAT flag and we could easily get lost while trying to determine which modification is which. How about indicating explicitly it's an exynos7 bits layout and renaming the flag to something like #define CLK_CPU_HAS_E7_MUX_STAT (1 << 16) ?