From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752317AbcGGMrI (ORCPT ); Thu, 7 Jul 2016 08:47:08 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:36592 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752202AbcGGMqr (ORCPT ); Thu, 7 Jul 2016 08:46:47 -0400 X-AuditID: cbfec7f5-f792a6d000001302-61-577e4f1d85ba Subject: Re: [PATCH v4 1/2] clk: exynos5433: do not use CLK_IGNORE_UNUSED for SPI clocks To: Andi Shyti , Chanwoo Choi References: <1467893637-12573-1-git-send-email-andi.shyti@samsung.com> <1467893637-12573-2-git-send-email-andi.shyti@samsung.com> Cc: Jaehoon Chung , Sylwester Nawrocki , Tomasz Figa , Michael Turquette , Stephen Boyd , Kukjin Kim , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andi Shyti From: Krzysztof Kozlowski Message-id: <577E4F1C.8070004@samsung.com> Date: Thu, 07 Jul 2016 14:46:20 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-version: 1.0 In-reply-to: <1467893637-12573-2-git-send-email-andi.shyti@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42I5/e/4ZV1Z/7pwg3n7rC22H3nGarH4x3Mm i+tfnrNa3PjVxmrx+oWhRf/j18wWmx5fY7X42HOP1eLyrjlsFjPO72OyuHjK1eLwm3ZWix9n ulksVu36w+jA5/H+Riu7x+W+XiaP60s+MXvsnHWX3WPTqk42j81L6j36tqxi9Pi8SS6AI4rL JiU1J7MstUjfLoEro/OBVcFEgYrnnRfZGxiP8XYxcnJICJhI7Nv0nQ3CFpO4cG89kM3FISSw lFFi493j7BDOM0aJ3j9LWEGqhAWiJLY9e8TSxcjBISLgKzF/mQZETTOjxOkVD5hAapgF5jBL rH/FDGKzCRhLbF6+BGwDr4CWxNR5G8HmsAioSpy8tpQdxBYViJCYtf0HE0SNoMSPyfdYQGxO AXeJz9eXsoLsYhbQk7h/UQtivLzE5jVvmScwCsxC0jELoWoWkqoFjMyrGEVTS5MLipPSc430 ihNzi0vz0vWS83M3MULi5+sOxqXHrA4xCnAwKvHwLsipDRdiTSwrrsw9xCjBwawkwrvRty5c iDclsbIqtSg/vqg0J7X4EKM0B4uSOO/MXe9DhATSE0tSs1NTC1KLYLJMHJxSDYxz27fUl14U ygvxkt4RZJZvEd3YevLogw/X3h9NU/9j420kuiUqtvmhXtBd2U2CJ91/Oql/MVn0wfHe91kf WWff3TJRzHp2ynrT7U1a7rvWyc6fL9Z6Nk15vqRE4rJZQvMzeNp7OGSc5ghFbzm9mU/aSZ3h eOmNk11Wv3ve3ZK/nWX7e4fG/y1KLMUZiYZazEXFiQAymCoAmwIAAA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/07/2016 02:13 PM, Andi Shyti wrote: > The CLK_IGNORE_UNUSED flag has to be avoided whenever possible. > Use the CLK_IS_CRITICAL flag instead for critical SPI1 clocks, > which enables the clock line during boot time. I don't agree. Both flags should be avoided. Clk is critical does not solve the problem. It is just a better workaround for lack of proper clock consumers. The IOCLK is not a critical clock. It can be disabled (e.g. when SoC is used on a board without any SPI device connected). Best regards, Krzysztof > > Suggested-by: Tomasz Figa > Signed-off-by: Andi Shyti > --- > drivers/clk/samsung/clk-exynos5433.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c > index c3a5318..337387b 100644 > --- a/drivers/clk/samsung/clk-exynos5433.c > +++ b/drivers/clk/samsung/clk-exynos5433.c > @@ -1662,7 +1662,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { > ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", > ENABLE_SCLK_PERIC, 12, > - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), > + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", > ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", > @@ -1677,7 +1677,7 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = { > GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, > 5, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, > - 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), > + 4, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, > 3, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", >