From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751427AbcGLIJv (ORCPT ); Tue, 12 Jul 2016 04:09:51 -0400 Received: from foss.arm.com ([217.140.101.70]:57352 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750999AbcGLIJs (ORCPT ); Tue, 12 Jul 2016 04:09:48 -0400 Subject: Re: [PATCH] irqchip/gicv3-its: Enable cacheable attribute Read-allocate hints To: Shanker Donthineni , linux-kernel , linux-arm-kernel References: <1468294608-30619-1-git-send-email-shankerd@codeaurora.org> Cc: Thomas Gleixner , Jason Cooper , Vikram Sethi , Philip Elcan From: Marc Zyngier Organization: ARM Ltd Message-ID: <5784A5C8.4080103@arm.com> Date: Tue, 12 Jul 2016 09:09:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.7.0 MIME-Version: 1.0 In-Reply-To: <1468294608-30619-1-git-send-email-shankerd@codeaurora.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Shanker, On 12/07/16 04:36, Shanker Donthineni wrote: > Read-allocation hints are not enabled for both the GIC-ITS and GICR > tables. This forces the hardware to always read the table contents > from an external memory (DDR) which is slow compared to cache memory. > Most of the tables are often read by hardware. So, it's better to > enable Read-allocate hints in addition to Write-allocate hints in > order to improve the GICR_PEND, GICR_PROP, Collection, Device, and > vCPU tables lookup time. While I'm not opposed to such a change, I'd like to see some evidence that this actually makes a difference. Have you measured an improvement on a particular implementation? If so, could you share your benchmarking method so that it could be be measured on others as well? Thanks, M. -- Jazz is not dead. It just smells funny...