From: Marc Zyngier <marc.zyngier@arm.com>
To: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>,
Bjorn Helgaas <bhelgaas@google.com>,
nofooter <nofooter@xilinx.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: PCIe MSI address is not written at pci_enable_msi_range call
Date: Wed, 20 Jul 2016 13:19:34 +0100 [thread overview]
Message-ID: <578F6C56.2090805@arm.com> (raw)
In-Reply-To: <8520D5D51A55D047800579B094147198258B896E@XAP-PVEXMBX01.xlnx.xilinx.com>
+tglx
On 13/07/16 09:33, Bharat Kumar Gogada wrote:
>> Subject: Re: PCIe MSI address is not written at pci_enable_msi_range call
>>
>> On 13/07/16 07:22, Bharat Kumar Gogada wrote:
>>>> Subject: Re: PCIe MSI address is not written at pci_enable_msi_range
>>>> call
>>>>
>>>> On 11/07/16 10:33, Bharat Kumar Gogada wrote:
>>>>> Hi Marc,
>>>>>
>>>>> Thanks for the reply.
>>>>>
>>>>> From PCIe Spec:
>>>>> MSI Enable Bit:
>>>>> If 1 and the MSI-X Enable bit in the MSI-X Message Control register
>>>>> (see Section 6.8.2.3) is 0, the function is permitted to use MSI to
>>>>> request service and is prohibited from using its INTx# pin.
>>>>>
>>>>> From Endpoint perspective, MSI Enable = 1 indicates MSI can be used
>>>> which means MSI address and data fields are available/programmed.
>>>>>
>>>>> In our SoC whenever MSI Enable goes from 0 --> 1 the hardware
>>>>> latches
>>>> onto MSI address and MSI data values.
>>>>>
>>>>> With current MSI implementation in kernel, our SoC is latching on to
>>>>> incorrect address and data values, as address/data are updated much
>>>>> later
>>>> than MSI Enable bit.
>>>>
>>>> As a side question, how does setting the affinity work on this
>>>> end-point if this involves changing the address programmed in the MSI
>> registers?
>>>> Do you expect the enabled bit to be toggled to around the write?
>>>>
>>>
>>> Yes,
>>
>> Well, that's pretty annoying, as this will not work either. But maybe your MSI
>> controller has a single doorbell? You haven't mentioned which HW that is...
>>
> The MSI address/data is located in config space, in our SoC for the logic behind PCIe
> to become aware of new address/data MSI enable transition is used (0 to 1).
> The logic cannot keep polling these registers in configuration space as it would consume power.
>
> So the logic uses the transition in MSI enable to latch on to address/data.
A couple of additional questions:
Does your HW support MSI masking? And if it does, does it resample the
address/data on unmask?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2016-07-20 12:19 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-11 2:32 PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada
2016-07-11 8:47 ` Marc Zyngier
2016-07-11 9:33 ` Bharat Kumar Gogada
2016-07-11 10:21 ` Marc Zyngier
2016-07-11 10:51 ` Bharat Kumar Gogada
2016-07-11 15:50 ` Marc Zyngier
2016-07-12 9:11 ` Bharat Kumar Gogada
2016-07-12 14:28 ` Marc Zyngier
2016-07-12 15:56 ` Marc Zyngier
2016-07-13 6:22 ` Bharat Kumar Gogada
2016-07-13 8:16 ` Marc Zyngier
2016-07-13 8:33 ` Bharat Kumar Gogada
2016-07-13 8:37 ` Marc Zyngier
2016-07-13 9:10 ` Bharat Kumar Gogada
2016-07-13 9:19 ` Marc Zyngier
2016-07-13 9:36 ` Bharat Kumar Gogada
2016-07-13 9:40 ` Marc Zyngier
2016-07-13 15:34 ` Bharat Kumar Gogada
2016-07-13 15:39 ` Marc Zyngier
2016-07-20 12:19 ` Marc Zyngier [this message]
2016-07-27 11:14 ` Bharat Kumar Gogada
-- strict thread matches above, loose matches on Subject: below --
2016-07-11 2:37 Bharat Kumar Gogada
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