From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932881AbcHKCkT (ORCPT ); Wed, 10 Aug 2016 22:40:19 -0400 Received: from regular1.263xmail.com ([211.150.99.131]:44767 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932582AbcHKCkQ (ORCPT ); Wed, 10 Aug 2016 22:40:16 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: zhengxing@rock-chips.com X-FST-TO: linux-arm-kernel@lists.infradead.org X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: <4c5b723bc6445ea61d50c7b8ab7447a0> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [v2 PATCH] clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical To: Guenter Roeck , Chris Zhong References: <1470765753-11619-1-git-send-email-zyw@rock-chips.com> Cc: =?UTF-8?Q?Heiko_St=c3=bcbner?= , =?UTF-8?B?5aea5pm65oOF?= , mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel , Tomasz Figa , "open list:ARM/Rockchip SoC..." , Douglas Anderson , Guenter Roeck , =?UTF-8?Q?St=c3=a9phane_Marchesin?= , wulf , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Xing Zheng Message-ID: <57ABE369.6070800@rock-chips.com> Date: Thu, 11 Aug 2016 10:31:05 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Chris, On 2016年08月11日 06:14, Guenter Roeck wrote: > On Tue, Aug 9, 2016 at 11:02 AM, Chris Zhong wrote: >> Fix incorrect rk3399 aclk_vio gating bit, it should be 0, not 10. With >> this modification, the aclk_vio_noc should be put into critical list, >> since it is required by VOP. >> And the Type-C DP need these clocks: aclk_hdcp_noc, hclk_hdcp_noc, >> pclk_hdcp_noc. Mark them as critical to avoid someone close them. >> >> Signed-off-by: Chris Zhong >> --- >> >> drivers/clk/rockchip/clk-rk3399.c | 6 +++++- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c >> index b173711a..676b017 100644 >> --- a/drivers/clk/rockchip/clk-rk3399.c >> +++ b/drivers/clk/rockchip/clk-rk3399.c >> @@ -1073,7 +1073,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { >> /* vio */ >> COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, >> RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, >> - RK3399_CLKGATE_CON(11), 10, GFLAGS), >> + RK3399_CLKGATE_CON(11), 0, GFLAGS), Sorry to broken copy&paste, thanks to fix the incorrect bit. Reviewed-by: Xing Zheng Thanks. >> COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0, >> RK3399_CLKSEL_CON(43), 0, 5, DFLAGS, >> RK3399_CLKGATE_CON(11), 1, GFLAGS), >> @@ -1470,6 +1470,9 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = { >> "aclk_cci_pre", >> "aclk_gic", >> "aclk_gic_noc", >> + "aclk_hdcp_noc", >> + "hclk_hdcp_noc", >> + "pclk_hdcp_noc", >> "pclk_perilp0", >> "pclk_perilp0", >> "hclk_perilp0", >> @@ -1489,6 +1492,7 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = { >> "gpll_hclk_perilp1_src", >> "gpll_aclk_perilp0_src", >> "gpll_aclk_perihp_src", >> + "aclk_vio_noc", > I think there was a previous comment suggesting that this clock should > be handled differently. Has this been resolved ? > > Otherwise > > Reviewed-by: Guenter Roeck > >> }; >> >> static const char *const rk3399_pmucru_critical_clocks[] __initconst = { >> -- >> 1.9.1 >> > > -- - Xing Zheng