From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752765AbcHOHOR (ORCPT ); Mon, 15 Aug 2016 03:14:17 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:24914 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751375AbcHOHOP (ORCPT ); Mon, 15 Aug 2016 03:14:15 -0400 Subject: Re: [PATCH 2/4] net: hix5hd2_gmac: add reset control and clock signals To: Rob Herring References: <1470906115-155569-1-git-send-email-lidongpo@hisilicon.com> <1470906115-155569-3-git-send-email-lidongpo@hisilicon.com> <20160812184824.GA8959@rob-hp-laptop> CC: , , , , , , , , , , , , , , , , From: Dongpo Li Message-ID: <57B16A43.4090600@hisilicon.com> Date: Mon, 15 Aug 2016 15:07:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20160812184824.GA8959@rob-hp-laptop> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.66.52.107] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.57B16A56.002D,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c91895dc623ef8e67e481181ce0751bd Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, On 2016/8/13 2:48, Rob Herring wrote: > On Thu, Aug 11, 2016 at 05:01:53PM +0800, Dongpo Li wrote: >> From: Li Dongpo >> >> Add three reset control signals, "mac_core_rst", "mac_ifc_rst" and >> "phy_rst". >> The following diagram explained how the reset signals work. >> >> SoC >> |----------------------------------------------------- >> | ------ | >> | | cpu | | >> | ------ | >> | | | >> | ------------ AMBA bus | >> | GMAC | | >> | ---------------------- | >> | ------------- mac_core_rst | -------------- | | >> | |clock and |-------------->| mac core | | | >> | |reset | | -------------- | | >> | |generator |---- | | | | >> | ------------- | | ---------------- | | >> | | ---------->| mac interface | | | >> | | mac_ifc_rst | ---------------- | | >> | | | | | | >> | | | ------------------ | | >> | |phy_rst | | RGMII interface | | | >> | | | ------------------ | | >> | | ---------------------- | >> |----------|------------------------------------------| >> | | >> | ---------- >> |--------------------- |PHY chip | >> ---------- >> >> The "mac_core_rst" represents "mac core reset signal", it resets >> the mac core including packet processing unit, descriptor processing unit, >> tx engine, rx engine, control unit. >> The "mac_ifc_rst" represents "mac interface reset signal", it resets >> the mac interface. The mac interface unit connects mac core and >> data interface like MII/RMII/RGMII. After we set a new value of >> interface mode, we must reset mac interface to reload the new mode value. >> The "phy_rst" represents "phy reset signal", it does a hardware reset >> on the PHY chip. This reset signal is optinal if the PHY can work well >> without the hardware reset. >> >> Add one more clock signal, the existing is MAC core clock, >> and the new one is MAC interface clock. >> >> Signed-off-by: Dongpo Li >> --- >> .../bindings/net/hisilicon-hix5hd2-gmac.txt | 16 ++- >> drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 140 +++++++++++++++++++-- >> 2 files changed, 143 insertions(+), 13 deletions(-) > > >> >> @@ -807,16 +829,26 @@ static int hix5hd2_net_open(struct net_device *dev) >> struct phy_device *phy; >> int ret; >> >> - ret = clk_prepare_enable(priv->clk); >> + ret = clk_prepare_enable(priv->mac_core_clk); >> + if (ret < 0) { >> + netdev_err(dev, "failed to enable mac core clk %d\n", ret); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(priv->mac_ifc_clk); >> if (ret < 0) { >> - netdev_err(dev, "failed to enable clk %d\n", ret); >> + clk_disable_unprepare(priv->mac_core_clk); >> + netdev_err(dev, "failed to enable mac ifc clk %d\n", ret); > > This change will break with existing DTs. The mac_ifc_clk should be > optional. > The mac_ifc_clk has existed in the existing hix5hd2. It's not implemented in the MAC driver because the CLOCK driver implements a "complex" ethernet clock type. So [PATCH 3/4] and [PATCH 4/4] are following this patch to change the CLOCK driver and existing DTs at the same time. > Rob > >> return ret; >> } > > . > Regards, Dongpo .