From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754908AbcHVMCx convert rfc822-to-8bit (ORCPT ); Mon, 22 Aug 2016 08:02:53 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:45745 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750809AbcHVMCv (ORCPT ); Mon, 22 Aug 2016 08:02:51 -0400 X-AuditID: cbfee68d-f79286d000007a9a-24-57bae9e8836c MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 8BIT Message-id: <57BAE9E8.50703@samsung.com> Date: Mon, 22 Aug 2016 21:02:48 +0900 From: Chanwoo Choi Organization: Samsung Electronics User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, k.kozlowski@samsung.com, chanwoo@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/2] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain References: <1471855308-12791-1-git-send-email-cw00.choi@samsung.com> In-reply-to: <1471855308-12791-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsWyRsSkUPfly13hBnNPMFlMvHGFxeL1C0OL /sevmS02Pb7GavGx5x6rxeVdc9gsZpzfx2Rx8ZSrxeE37awWP850s1is2vWH0YHb4/2NVnaP y329TB47Z91l99i0qpPNY/OSeo++LasYPT5vkgtgj+KySUnNySxLLdK3S+DKuLTmDmPBHd6K mR8fMjUwdnF0MXJySAiYSCyfdIgdwhaTuHBvPVsXIxeHkMAKRomO2QuZYYr+rdgMlZjFKNFy 5gsTSIJXQFDix+R7LCA2s4C6xKR5i5ghbBGJN52voOLaEssWvmaGaH7AKHH45jNmiGYNid6j m8CKWARUJTb/2gEWZxPQktj/4gYbiM0voChx9cdjxi5GDg5RgQiJ7hOVIKaIgKHEzUNKICOZ BX4wSjTPecYKUi4sECKxa/lydohdsxklVmyYBzaHU8BNon/lCVaIb3o5JJafdILYKyDxbfIh FpChEgKyEpsOQD0sKXFwxQ2WCYwSs5C8OQvJm7OQvDkLyZsLGFlWMYqmFiQXFCelFxnqFSfm Fpfmpesl5+duYgRG/el/z3p3MN4+YH2IUYCDUYmH98H9XeFCrIllxZW5hxhNgS6ayCwlmpwP TC15JfGGxmZGFqYmpsZG5pZmSuK8ilI/g4UE0hNLUrNTUwtSi+KLSnNSiw8xMnFwSjUwOu49 rGmgVfvy4tvLTxcyr/h4L/+LAyursn9Rwd5PJuusdmnHXlRtmTy5jz2tfUPP2Z7GtZs9Y/9J zvw2YX3q3AcKb8pkzqu9EWBl+1/VrRKi+a9h81rRS63TdUSus/8Kbtboj/vD/V7xeebtSUdE Fu25ueDwOstnl6/cKHk+xyznK9dv1d3Bn5RYijMSDbWYi4oTAfm8ZND1AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKKsWRmVeSWpSXmKPExsVy+t9jQd0XL3eFG+w8Ymkx8cYVFovXLwwt +h+/ZrbY9Pgaq8XHnnusFpd3zWGzmHF+H5PFxVOuFofftLNa/DjTzWKxatcfRgduj/c3Wtk9 Lvf1MnnsnHWX3WPTqk42j81L6j36tqxi9Pi8SS6APaqB0SYjNTEltUghNS85PyUzL91WyTs4 3jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH6EQlhbLEnFKgUEBicbGSvh2mCaEhbroWMI0R ur4hQXA9RgZoIGENY8a5xklMBad4K5bs52hg/MHexcjJISFgIvFvxWY2CFtM4sK99UA2F4eQ wCxGiZYzX5hAErwCghI/Jt9j6WLk4GAWkJc4cikbJMwsoC4xad4iZoj6B4wSh28+Y4ao15Do PbqJBcRmEVCV2PxrB1icTUBLYv+LG2DL+AUUJa7+eMwIMlNUIEKi+0QliCkiYChx85ASyEhm gR+MEs1znrGClAsLhEjsWr6cHWLXbEaJFRvmgc3hFHCT6F95gnUCo+AsJKfOQjh1FpJTFzAy r2KUSC1ILihOSs81zEst1ytOzC0uzUvXS87P3cQIThLPpHYwHtzlfohRgINRiYf3xbNd4UKs iWXFlbmHGCU4mJVEeMWAKUaINyWxsiq1KD++qDQntfgQoynQrxOZpUST84EJLK8k3tDYxMzI 0sjc0MLI2FxJnPfx/3VhQgLpiSWp2ampBalFMH1MHJxSDYyeGW42Cz88b1D5y3izrI/l5JOc 3XdOpHVFv+JeZLye1XfebsvOzzq/+6WDz/9/HJfsuOD55ANv7Fa1NfziD+OP5T2QzS2/P333 zOfTH5zkyYmfX5RhfbmGoYJtn//Wx/u31oWemiyysn23IEM9x9S+mAT3+ZPPhP9LztRbu+2r tfjRySl/+B4rsRRnJBpqMRcVJwIA/uhNdCgDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear all, Please ignore this patches because the CMU_CDREX should support the 800MHz DRAM clock. But, following clk_summary show the 825MHz clock. So, I need to change the clock rate of fout_bpll or check it. After setting the DRAM clock as 800MHz, I'll send the patches again. Regards, Chanwoo Choi On 2016년 08월 22일 17:41, Chanwoo Choi wrote: > This patches add the clocks for CMU_CDREX (DRAM Express Controller) > that generates the clocks for DRAM and NoC (Network on Chip) bus clock. > > [Result for clk_summary on exynos5422-odroidxu3 board] > fout_bpll 0 0 825000000 0 0 > mout_bpll 0 0 825000000 0 0 > mout_mclk_cdrex 0 0 825000000 0 0 > dout_pclk_core_mem 0 0 206250000 0 0 > dout_sclk_cdrex 0 0 825000000 0 0 > dout_clk2x_phy0 0 0 825000000 0 0 > dout_aclk_cdrex1 0 0 412500000 0 0 > dout_pclk_cdrex 0 0 103125000 0 0 > dout_cclk_drex0 0 0 412500000 0 0 > > Chanwoo Choi (2): > dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) > clk: samsung: exynos5420: Add clocks for CMU_CDREX domain > > drivers/clk/samsung/clk-exynos5420.c | 35 ++++++++++++++++++++++++++++++++++ > include/dt-bindings/clock/exynos5420.h | 11 ++++++++++- > 2 files changed, 45 insertions(+), 1 deletion(-) >