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Date: Fri, 26 Aug 2016 18:49:16 +0800
From: Xing Zheng <zhengxing@rock-chips.com>
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To: Shawn Lin <shawn.lin@rock-chips.com>
CC: linux-rockchip@lists.infradead.org, huangtao@rock-chips.com,
        Mark Rutland <mark.rutland@arm.com>,
        Elaine Zhang <zhangqing@rock-chips.com>,
        Heiko Stuebner <heiko@sntech.de>, devicetree@vger.kernel.org,
        Catalin Marinas <catalin.marinas@arm.com>,
        Brian Norris <briannorris@chromium.org>,
        Will Deacon <will.deacon@arm.com>, dianders@chromium.org,
        linux-kernel@vger.kernel.org,
        Masahiro Yamada <yamada.masahiro@socionext.com>,
        Rob Herring <robh+dt@kernel.org>, David Wu <david.wu@rock-chips.com>,
        jay.xu@rock-chips.com, linux-arm-kernel@lists.infradead.org,
        Caesar Wang <wxt@rock-chips.com>
Subject: Re: [PATCH] arm64: dts: rockchip: fix the address map for WDT0 and
 WDT1
References: <1472192551-16754-1-git-send-email-zhengxing@rock-chips.com> <607537bf-1c49-d7e0-ead9-8c1e6164e44e@rock-chips.com>
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Hi Shawn,

On 2016年08月26日 17:41, Shawn Lin wrote:
> On 2016/8/26 14:22, Xing Zheng wrote:
>> Dues to incorrect description in the TRM, the WDTs base address
>> should be fixed and swap them like this:
>> WDT0 - 0xff848000
>> WDT1 - 0xff840000
>>
>> And, it is right that only WDT0 can generate global software reset.
>> We will update the TRM to fix it.
>>
>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>> ---
>>
>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
>> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> index bc86e8c..f0f52c1 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> @@ -1002,9 +1002,9 @@
>> };
>> };
>>
>> - watchdog@ff840000 {
>> + watchdog@ff848000 {
>
> Just a nit, should we mark this explicitly as "watchdog0" ?
> I still need to look up for which wdt you are using.:)
Done.

Thanks.
>
>> compatible = "snps,dw-wdt";
>> - reg = <0x0 0xff840000 0x0 0x100>;
>> + reg = <0x0 0xff848000 0x0 0x100>;
>> clocks = <&cru PCLK_WDT>;
>> interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
>> };
>>
>
>


-- 
- Xing Zheng