From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759621AbcHaIhZ (ORCPT ); Wed, 31 Aug 2016 04:37:25 -0400 Received: from foss.arm.com ([217.140.101.70]:55118 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759155AbcHaIgN (ORCPT ); Wed, 31 Aug 2016 04:36:13 -0400 Subject: Re: [PATCH] generic: Add the exception case checking routine for ppi interrupt To: "majun (F)" , Mark Rutland References: <1472530639-21616-1-git-send-email-majun258@huawei.com> <57C548D0.3090700@arm.com> <57C5617B.6080801@huawei.com> <57C568F8.20802@arm.com> <20160830112113.GE1223@leverpostej> <57C67ABE.908@huawei.com> Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@linutronix.de, dingtianhong@huawei.com, guohanjun@huawei.com From: Marc Zyngier X-Enigmail-Draft-Status: N1110 Organization: ARM Ltd Message-ID: <57C696DA.4090301@arm.com> Date: Wed, 31 Aug 2016 09:35:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.7.0 MIME-Version: 1.0 In-Reply-To: <57C67ABE.908@huawei.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/08/16 07:35, majun (F) wrote: > Hi Marc & Mark: > > 在 2016/8/30 19:21, Mark Rutland 写道: >> On Tue, Aug 30, 2016 at 12:07:36PM +0100, Marc Zyngier wrote: >>> +Mark >>> On 30/08/16 11:35, majun (F) wrote: >>>> 在 2016/8/30 16:50, Marc Zyngier 写道: >>>>> On 30/08/16 05:17, MaJun wrote: >>>>>> From: Ma Jun >>>>>> >>>>>> During system booting, if the interrupt which has no action registered >>>>>> is triggered, it would cause system panic when try to access the >>>>>> action member. >>>>> >>>>> And why would that interrupt be enabled? If you enable a PPI before >>>>> registering a handler, you're doing something wrong. >>>> >>>> Actually,the problem described above happened during the capture >>>> kernel booting. >>>> >>>> In my system, sometimes there is a pending physical timer >>>> interrupt(30) when the first kernel panic and the status is kept >>>> until the capture kernel booting. >>> >>> And that's perfectly fine. The interrupt can be pending forever, as it >>> shouldn't get enabled. >>> >>>> So, this interrupt will be handled during capture kernel booting. >>> >>> Why? Who enables it? >>> >>>> Becasue we use virt timer interrupt but not physical timer interrupt >>>> in capture kernel, the interrupt 30 has no action handler. >>> >>> Again: who enables this interrupt? Whichever driver enables it should be >>> fixed. >> >> I'm also at a loss. >> >> In this case, arch_timer_uses_ppi must be VIRT_PPI. So in >> arch_timer_register(), we'll only request_percpu_irq the virt PPI. >> arch_timer_has_nonsecure_ppi() will be false, given arch_timer_uses_ppi >> is VIRT_PPI, so in arch_timer_starting_cpu() we'll only >> enable_percpu_irq() the virt PPI. >> >> We don't fiddle with arch_timer_uses_ppi after calling >> arch_timer_register(). So I can't see how we could enable another IRQ in >> this case. >> >> Looking at the driver in virt/kvm/arm/arch_timer.c, we only enable what >> we've succesfully requested, so it doesnt' seem like there's an issue >> there. >> >> >From a quick look at teh GIC driver, it looks like we reset PPIs >> correctly, so it doesn't look like we have a "latent enable". >> > > I just checked the status of irq 30 during capture kernel booting. > > The irq 30 status is: mask, pending after arch_timer_starting_cpu() called. > Because irq 30 triggered only 1 time during capture kernel booting, > I think this problem maybe happened in the case like: > 1:irq 30 triggered, but not acked by cpu yet. > 2:local_irq_disable() called > 3:system reboot -->capture kernel booting > 4:local_irq_enable() > 5:irq 30 acked by CPU. > > Is this case possible? I can't see how, because you've missed: 3b: All PPIs are disabled as each CPU comes up So for (5) to occur, I can only see two possibilities: (a) either something else is enabling the timer PPI (b) your GIC doesn't correctly retire a pending PPI that is being disabled I'm discounting (b) because I can't see how the system would work otherwise, so (a) must be happening somehow. Thanks, M. -- Jazz is not dead. It just smells funny...