From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751716AbcIAIQk (ORCPT ); Thu, 1 Sep 2016 04:16:40 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:63616 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750846AbcIAIQg (ORCPT ); Thu, 1 Sep 2016 04:16:36 -0400 Subject: Re: [PATCH] generic: Add the exception case checking routine for ppi interrupt To: Marc Zyngier , Mark Rutland References: <1472530639-21616-1-git-send-email-majun258@huawei.com> <57C548D0.3090700@arm.com> <57C5617B.6080801@huawei.com> <57C568F8.20802@arm.com> <20160830112113.GE1223@leverpostej> <57C67ABE.908@huawei.com> <57C696DA.4090301@arm.com> CC: , , , , , From: "majun (F)" Message-ID: <57C7E3B6.1040605@huawei.com> Date: Thu, 1 Sep 2016 16:15:50 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 MIME-Version: 1.0 In-Reply-To: <57C696DA.4090301@arm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.177.235.245] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.57C7E3C3.01F4,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f03481f8ad3d52aa70d270cc074d98cf Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2016/8/31 16:35, Marc Zyngier 写道: > On 31/08/16 07:35, majun (F) wrote: [...] >>> >> >> I just checked the status of irq 30 during capture kernel booting. >> >> The irq 30 status is: mask, pending after arch_timer_starting_cpu() called. >> Because irq 30 triggered only 1 time during capture kernel booting, >> I think this problem maybe happened in the case like: >> 1:irq 30 triggered, but not acked by cpu yet. >> 2:local_irq_disable() called >> 3:system reboot -->capture kernel booting >> 4:local_irq_enable() >> 5:irq 30 acked by CPU. >> >> Is this case possible? > > I can't see how, because you've missed: > > 3b: All PPIs are disabled as each CPU comes up > > So for (5) to occur, I can only see two possibilities: > (a) either something else is enabling the timer PPI I checked the whole process, the irq 30 alway keeping disabled. > (b) your GIC doesn't correctly retire a pending PPI that is being disabled According to our hardware guy said, GIC in our system has problem in this case. Usually, when we mask irq 30, the interrupt which in pending status but not acked by cpu should be released/cleared by hardware, but actually, we did't do like this in our system. So, this conclusion just same as you assumption. Do you have any suggestion or workaround for this problem? Thanks! Majun > > I'm discounting (b) because I can't see how the system would work > otherwise, so (a) must be happening somehow. > > Thanks, > > M. >