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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250206043055.177004-1-kylehendrydev@gmail.com> <1317d50b-8302-4936-b56c-7a9f5b3970b9@broadcom.com> <9bd9c1e4-2401-46bd-937f-996e97d750c5@lunn.ch> <318e8b95-4ef8-43ca-a19d-129372a9dc48@gmail.com> Content-Language: en-US From: Florian Fainelli Autocrypt: addr=florian.fainelli@broadcom.com; keydata= xsBNBFPAG8ABCAC3EO02urEwipgbUNJ1r6oI2Vr/+uE389lSEShN2PmL3MVnzhViSAtrYxeT M0Txqn1tOWoIc4QUl6Ggqf5KP6FoRkCrgMMTnUAINsINYXK+3OLe7HjP10h2jDRX4Ajs4Ghs JrZOBru6rH0YrgAhr6O5gG7NE1jhly+EsOa2MpwOiXO4DE/YKZGuVe6Bh87WqmILs9KvnNrQ PcycQnYKTVpqE95d4M824M5cuRB6D1GrYovCsjA9uxo22kPdOoQRAu5gBBn3AdtALFyQj9DQ KQuc39/i/Kt6XLZ/RsBc6qLs+p+JnEuPJngTSfWvzGjpx0nkwCMi4yBb+xk7Hki4kEslABEB AAHNMEZsb3JpYW4gRmFpbmVsbGkgPGZsb3JpYW4uZmFpbmVsbGlAYnJvYWRjb20uY29tPsLB IQQQAQgAywUCZWl41AUJI+Jo+hcKAAG/SMv+fS3xUQWa0NryPuoRGjsA3SAUAAAAAAAWAAFr ZXktdXNhZ2UtbWFza0BwZ3AuY29tjDAUgAAAAAAgAAdwcmVmZXJyZWQtZW1haWwtZW5jb2Rp bmdAcGdwLmNvbXBncG1pbWUICwkIBwMCAQoFF4AAAAAZGGxkYXA6Ly9rZXlzLmJyb2FkY29t Lm5ldAUbAwAAAAMWAgEFHgEAAAAEFQgJChYhBNXZKpfnkVze1+R8aIExtcQpvGagAAoJEIEx tcQpvGagWPEH/2l0DNr9QkTwJUxOoP9wgHfmVhqc0ZlDsBFv91I3BbhGKI5UATbipKNqG13Z TsBrJHcrnCqnTRS+8n9/myOF0ng2A4YT0EJnayzHugXm+hrkO5O9UEPJ8a+0553VqyoFhHqA zjxj8fUu1px5cbb4R9G4UAySqyeLLeqnYLCKb4+GklGSBGsLMYvLmIDNYlkhMdnnzsSUAS61 WJYW6jjnzMwuKJ0ZHv7xZvSHyhIsFRiYiEs44kiYjbUUMcXor/uLEuTIazGrE3MahuGdjpT2 IOjoMiTsbMc0yfhHp6G/2E769oDXMVxCCbMVpA+LUtVIQEA+8Zr6mX0Yk4nDS7OiBlvOwE0E U8AbwQEIAKxr71oqe+0+MYCc7WafWEcpQHFUwvYLcdBoOnmJPxDwDRpvU5LhqSPvk/yJdh9k 4xUDQu3rm1qIW2I9Puk5n/Jz/lZsqGw8T13DKyu8eMcvaA/irm9lX9El27DPHy/0qsxmxVmU pu9y9S+BmaMb2CM9IuyxMWEl9ruWFS2jAWh/R8CrdnL6+zLk60R7XGzmSJqF09vYNlJ6Bdbs MWDXkYWWP5Ub1ZJGNJQ4qT7g8IN0qXxzLQsmz6tbgLMEHYBGx80bBF8AkdThd6SLhreCN7Uh IR/5NXGqotAZao2xlDpJLuOMQtoH9WVNuuxQQZHVd8if+yp6yRJ5DAmIUt5CCPcAEQEAAcLB gQQYAQIBKwUCU8AbwgUbDAAAAMBdIAQZAQgABgUCU8AbwQAKCRCTYAaomC8PVQ0VCACWk3n+ obFABEp5Rg6Qvspi9kWXcwCcfZV41OIYWhXMoc57ssjCand5noZi8bKg0bxw4qsg+9cNgZ3P N/DFWcNKcAT3Z2/4fTnJqdJS//YcEhlr8uGs+ZWFcqAPbteFCM4dGDRruo69IrHfyyQGx16s CcFlrN8vD066RKevFepb/ml7eYEdN5SRALyEdQMKeCSf3mectdoECEqdF/MWpfWIYQ1hEfdm C2Kztm+h3Nkt9ZQLqc3wsPJZmbD9T0c9Rphfypgw/SfTf2/CHoYVkKqwUIzI59itl5Lze+R5 wDByhWHx2Ud2R7SudmT9XK1e0x7W7a5z11Q6vrzuED5nQvkhAAoJEIExtcQpvGagugcIAJd5 EYe6KM6Y6RvI6TvHp+QgbU5dxvjqSiSvam0Ms3QrLidCtantcGT2Wz/2PlbZqkoJxMQc40rb fXa4xQSvJYj0GWpadrDJUvUu3LEsunDCxdWrmbmwGRKqZraV2oG7YEddmDqOe0Xm/NxeSobc MIlnaE6V0U8f5zNHB7Y46yJjjYT/Ds1TJo3pvwevDWPvv6rdBeV07D9s43frUS6xYd1uFxHC 7dZYWJjZmyUf5evr1W1gCgwLXG0PEi9n3qmz1lelQ8lSocmvxBKtMbX/OKhAfuP/iIwnTsww 95A2SaPiQZA51NywV8OFgsN0ITl2PlZ4Tp9hHERDe6nQCsNI/Us= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2/9/25 15:30, Andrew Lunn wrote: > On Fri, Feb 07, 2025 at 08:44:31AM -0800, Florian Fainelli wrote: >> On 2/6/25 17:41, Kyle Hendry wrote: >>> >>> On 2025-02-06 12:17, Andrew Lunn wrote: >>>> On Thu, Feb 06, 2025 at 10:15:50AM -0800, Florian Fainelli wrote: >>>>> Hi Kyle, >>>>> >>>>> On 2/5/25 20:30, Kyle Hendry wrote: >>>>>> Some BCM63268 bootloaders do not enable the internal PHYs by default. >>>>>> This patch series adds functionality for the switch driver to >>>>>> configure the gigabit ethernet PHY. >>>>>> >>>>>> Signed-off-by: Kyle Hendry >>>>> So the register address you are manipulating logically belongs >>>>> in the GPIO >>>>> block (GPIO_GPHY_CTRL) which has become quite a bit of a sundry here. I >>>>> don't have a strong objection about the approach picked up here >>>>> but we will >>>>> need a Device Tree binding update describing the second (and optional) >>>>> register range. >>>> Despite this being internal, is this actually a GPIO? Should it be >>>> modelled as a GPIO line connected to a reset input on the PHY? It >>>> would then nicely fit in the existing phylib handling of a PHY with a >>>> GPIO reset line? >>>> >>>>     Andrew >>> The main reason I took this approach is because a SF2 register has >>> similar bits and I wanted to be consistent with that driver. If it >>> makes more sense to treat these bits as GPIOs/clocks/resets then it >>> would make the implementation simpler. >> >> I don't think there is a need to go that far, and I don't think any of those >> abstractions work really well in the sense that they are neither clocks, nor >> resets, nor GPIOs, they are just enable bits for the power gating logic of >> the PHY, power domains would be the closest to what this is, but this is a >> very heavy handed approach with little benefit IMHO. > > O.K. The naming is not particularly helpful. It is in the GPIO block, > and named GPIO_GPHY_CTRL so it kind of sounds like a GPIO. If the > existing GPIO driver could expose it as a GPIO it would of been a lot > simpler. You are no stranger to what HW designers like to do: use whatever existing hardware block already exists to add random enable and status bits to control whatever they fancy that was not exposed before. This happens whenever SW/FW people don't push back and ask for proper compartmentalization and abstractions to be used. Sometimes layout and schedule also play a role, but more often than not, it's "just software" so you can update to to account for the fact that bit is there, and not here, right? This one is exactly what happened: there was spare room in the decoding address space of the register block, so it was natural from there to add a 32-bit word that would hold the enable bits for the internal Gigabit PHY... Those bits are not GPIOs, they are just simple enable/control bits feeding an internal signal. > > If the SF2 has similar bits, could the SF2 code be shared? The SF2 single GPHY control register is different and more standardized in many ways, so I don't see much value in sharing that code. The SWITCH_REG register block in that case does follow a consistent layout across different product lines. -- Florian