From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752260AbdADFr3 (ORCPT ); Wed, 4 Jan 2017 00:47:29 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:10947 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750970AbdADFrZ (ORCPT ); Wed, 4 Jan 2017 00:47:25 -0500 Subject: Re: [RFC PATCH] ACPI/PCI: Fix bus range comparation in pci_mcfg_lookup To: Lorenzo Pieralisi References: <1482397663-98715-1-git-send-email-wangzhou1@hisilicon.com> <20170103120021.GC7145@red-moon> CC: "Rafael J. Wysocki" , Len Brown , Tomasz Nowicki , Jayachandran C , jorn Helgaas , , , , , From: Zhou Wang Message-ID: <586C8BCC.7020006@hisilicon.com> Date: Wed, 4 Jan 2017 13:44:44 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20170103120021.GC7145@red-moon> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.63.139.185] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.586C8BD8.0029,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9d1e142a0fcf5cbff08ffec262c185dc Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2017/1/3 20:00, Lorenzo Pieralisi wrote: > On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote: >> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each >> host bridge should be in the coverage of bus range of related PCIe segment. >> >> This patch will support this kind of scenario: >> >> MCFG: >> bus range: 0x00~0xff. >> segment: 0. >> DSDT: >> host bridge 1: >> bus range: 0x00~0x1f. >> segment: 0. >> host bridge 2: >> bus range: 0x20~0x4f. >> segment: 0. > > "The configuration data provided by an MCFG region (ie PCI segment and > bus range) may span multiple host bridges. > > Current code in pci_mcfg_lookup() carries out an exact match of host > bridge bus range start value against the MCFG region(s) bus range start > value which would cause configurations like the following: > > MCFG region: > bus range: 0x00~0xff. > segment: 0. > > PCI host bridges configuration (segment numbers and bus ranges): > host bridge 1: > bus range: 0x00~0x1f. > segment: 0. > host bridge 2: > bus range: 0x20~0x4f. > segment: 0. > > to fail, in that the bus range start value for host bridge 2 does > not match the bus range start value of the respective MCFG region. > > Relax the bus range check in pci_mcfg_lookup() to cater for > PCI configurations with multiple host bridges sharing the same > MCFG region." > > Acked-by: Lorenzo Pieralisi Hi Lorenzo, Thanks for your view. I will modify the commit message and post a new version patch. Regards, Zhou > >> Signed-off-by: Zhou Wang >> --- >> drivers/acpi/pci_mcfg.c | 5 ++--- >> 1 file changed, 2 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c >> index b5b376e..46a3e32 100644 >> --- a/drivers/acpi/pci_mcfg.c >> +++ b/drivers/acpi/pci_mcfg.c >> @@ -40,11 +40,10 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res) >> struct mcfg_entry *e; >> >> /* >> - * We expect exact match, unless MCFG entry end bus covers more than >> - * specified by caller. >> + * We expect the range in bus_res in the coverage of MCFG bus range. >> */ >> list_for_each_entry(e, &pci_mcfg_list, list) { >> - if (e->segment == seg && e->bus_start == bus_res->start && >> + if (e->segment == seg && e->bus_start <= bus_res->start && >> e->bus_end >= bus_res->end) >> return e->addr; >> } >> -- >> 1.9.1 >> > > . >