From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750761AbdALFrs (ORCPT ); Thu, 12 Jan 2017 00:47:48 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:36295 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750698AbdALFrp (ORCPT ); Thu, 12 Jan 2017 00:47:45 -0500 Subject: Re: [PATCH v3 04/10] Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event counting. To: Mark Rutland References: <1483339777-23973-1-git-send-email-anurup.m@huawei.com> <20170110175500.GD24036@leverpostej> Cc: corbet@lwn.net, will.deacon@arm.com, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com, zhangshaokun@hisilicon.com, tanxiaojun@huawei.com, xuwei5@hisilicon.com, sanil.kumar@hisilicon.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, shiju.jose@huawei.com, linuxarm@huawei.com, shyju.pv@huawei.com, dikshit.n@huawei.com From: Anurup M Message-ID: <58771879.2010604@gmail.com> Date: Thu, 12 Jan 2017 11:17:37 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20170110175500.GD24036@leverpostej> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 10 January 2017 11:25 PM, Mark Rutland wrote: > On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote: >> +The Hisilicon SoC HiP05/06/07 chips consist of various independent system >> +device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN). >> +These PMU devices are independent and have hardware logic to gather >> +statistics and performance information. >> + >> +HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is >> +called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL >> +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. >> +Each SCCL has 1 L3 cache and 1 MN units. > Are there systems with multiple SCCLs? Or is there only one SCCL per > system? The HiP0x are encapsulated by multiple SCCL (CPU die) and SICL (IO die). The HiP06 and HiP07 have two SCCLs. >> +The L3 cache is shared by all CPU cores in a CPU die. The L3C has four banks >> +(or instances). Each bank or instance of L3C has Eight 32-bit counter >> +registers and also event control registers. The HiP05/06 chip L3 cache has >> +22 statistics events. The HiP07 chip has 66 statistics events. These events >> +are very useful for debugging. > Is an L3C associated with a subset of physical memory (as with the ARM > CCN's L3C), or is it associated with a set of CPUs (e.g. only those in > a single SCCL) covering all physical memory (as with each CPU's L1 & > L2)? Yes the L3C is associated with the set of CPUs in a single SCCL covering all physical memory. The L3 cache in all the SCCLs share the complete physical memory. Thanks, Anurup > Thanks, > Mark.