* [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399
@ 2017-01-18 4:20 Xing Zheng
2017-01-18 4:27 ` hl
2017-01-18 10:25 ` Heiko Stübner
0 siblings, 2 replies; 3+ messages in thread
From: Xing Zheng @ 2017-01-18 4:20 UTC (permalink / raw)
To: heiko
Cc: dianders, linux-rockchip, hl, Xing Zheng, Michael Turquette,
Stephen Boyd, linux-clk, linux-arm-kernel, linux-kernel
The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5.
Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3399.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 3490887..73121b14 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(11), 8, GFLAGS),
COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
- RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
RK3399_CLKGATE_CON(11), 11, GFLAGS),
GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 12, GFLAGS),
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399
2017-01-18 4:20 [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399 Xing Zheng
@ 2017-01-18 4:27 ` hl
2017-01-18 10:25 ` Heiko Stübner
1 sibling, 0 replies; 3+ messages in thread
From: hl @ 2017-01-18 4:27 UTC (permalink / raw)
To: Xing Zheng, heiko
Cc: dianders, linux-rockchip, Michael Turquette, Stephen Boyd,
linux-clk, linux-arm-kernel, linux-kernel
Tested-by: Lin Huang <hl@rock-chips.com>
On 2017年01月18日 12:20, Xing Zheng wrote:
> The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5.
>
> Reported-by: Lin Huang <hl@rock-chips.com>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> ---
>
> drivers/clk/rockchip/clk-rk3399.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index 3490887..73121b14 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
> RK3399_CLKGATE_CON(11), 8, GFLAGS),
>
> COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
> - RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
> + RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
> RK3399_CLKGATE_CON(11), 11, GFLAGS),
> GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
> RK3399_CLKGATE_CON(32), 12, GFLAGS),
--
Lin Huang
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399
2017-01-18 4:20 [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399 Xing Zheng
2017-01-18 4:27 ` hl
@ 2017-01-18 10:25 ` Heiko Stübner
1 sibling, 0 replies; 3+ messages in thread
From: Heiko Stübner @ 2017-01-18 10:25 UTC (permalink / raw)
To: Xing Zheng
Cc: dianders, linux-rockchip, hl, Michael Turquette, Stephen Boyd,
linux-clk, linux-arm-kernel, linux-kernel
Am Mittwoch, 18. Januar 2017, 12:20:56 CET schrieb Xing Zheng:
> The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5.
>
> Reported-by: Lin Huang <hl@rock-chips.com>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
applied for 4.11 with Lin's test tag
Thanks
Heiko
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-01-18 4:20 [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399 Xing Zheng
2017-01-18 4:27 ` hl
2017-01-18 10:25 ` Heiko Stübner
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