From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750945AbdAXNkl (ORCPT ); Tue, 24 Jan 2017 08:40:41 -0500 Received: from szxga03-in.huawei.com ([119.145.14.66]:32123 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750753AbdAXNkj (ORCPT ); Tue, 24 Jan 2017 08:40:39 -0500 Subject: [RFC 0/4] irqchip, gicv3-its: Workaround for hisilicon 161010801 erratum(bypass SMMU for MSI) References: <588625CB.5060303@huawei.com> To: , , CC: , , , , , From: Shameerali Kolothum Thodi X-Forwarded-Message-Id: <588625CB.5060303@huawei.com> Message-ID: <5887593A.201@huawei.com> Date: Tue, 24 Jan 2017 13:40:10 +0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <588625CB.5060303@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On certain HiSilicon platforms (Hip05/Hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a quirk to bypass the SMMU MSI transactions on these platforms.The quirk is implemented in GICv3 ITS driver. On top of this, the GICv3 ITS IIDR register is not populated correctly on these platforms and this makes it difficult to use the existing IIDR based quirk implementation in the GICv3 ITS driver. This patch series adds a quirk mechanism based on device tree binding or ACPI OEM information. shameer (4): irqchip, gicv3-its: Add device tree binding for hisilicon 161010801 erratum irqchip, gicv3-its:Workaround for HiSilicon erratum 161010801 irqchip, gicv3-its: Introduce ACPI generic quirk framework irqchip, gicv3-its: Add HiSilicon acpi based erratum data. .../bindings/interrupt-controller/arm,gic-v3.txt | 6 ++ arch/arm64/Kconfig | 15 +++ drivers/irqchip/irq-gic-common.h | 1 + drivers/irqchip/irq-gic-v3-its.c | 117 ++++++++++++++++++++- 4 files changed, 138 insertions(+), 1 deletion(-) -- 1.9.1