From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751050AbdAXNoo (ORCPT ); Tue, 24 Jan 2017 08:44:44 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:19694 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750822AbdAXNom (ORCPT ); Tue, 24 Jan 2017 08:44:42 -0500 Subject: [RFC 1/4] irqchip, gicv3-its: Add device tree binding for hisilicon 161010801 erratum References: <588625E3.9040703@huawei.com> To: , , CC: , , , , From: Shameerali Kolothum Thodi X-Forwarded-Message-Id: <588625E3.9040703@huawei.com> Message-ID: <588759E0.1010804@huawei.com> Date: Tue, 24 Jan 2017 13:42:56 +0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.2.0 MIME-Version: 1.0 In-Reply-To: <588625E3.9040703@huawei.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.588759F2.00C2,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 413151c51cfee22ffd8adf4ffbb7b509 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This erratum describes the limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions and on those platforms the MSI transactions has to be bypassed by SMMU. The IIDR register of the GICv3 ITS on these platforms are not properly populated to differentiate the hardware, hence describe it in device tree. Signed-off-by: shameer --- .../devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cda..84af301 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,12 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optional +- hisilicon,erratum-161010801 : A boolean property. Indicates the presence of + erratum 161010801, which says that these platforms doesn't support SMMU + mapping for MSI transactions and those transactions has to be bypassed + by SMMU. + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. -- 1.9.1