From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 173B8C10F1B for ; Tue, 27 Dec 2022 10:31:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229844AbiL0Kba (ORCPT ); Tue, 27 Dec 2022 05:31:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229445AbiL0KbX (ORCPT ); Tue, 27 Dec 2022 05:31:23 -0500 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0849D3 for ; Tue, 27 Dec 2022 02:31:20 -0800 (PST) Received: from [80.120.31.194] (helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1pA7Ek-0004nx-Jl; Tue, 27 Dec 2022 11:31:10 +0100 From: Heiko Stuebner To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Nathan Chancellor , Icenowy Zheng Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Icenowy Zheng Subject: Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Date: Tue, 27 Dec 2022 11:31:09 +0100 Message-ID: <5894419.tdWV9SEqCh@phil> In-Reply-To: <20221227020258.303900-1-uwu@icenowy.me> References: <20221227020258.303900-1-uwu@icenowy.me> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 27. Dezember 2022, 03:02:57 CET schrieb Icenowy Zheng: > The dcache.cva encoding shown in the comments are wrong, it's for > dcache.cval1 (which is restricted to L1) instead. > > Fix this in the comment and in the hardcoded instruction. > > Signed-off-by: Icenowy Zheng > --- > The code is tested on a LiteX SoC with OpenC906 core, and it > successfully boots to Systemd on a SD card connected to LiteSDCard. > > This change should be not noticable on C906, but on multi-core C910 > cluster it should fixes something. Unfortunately TH1520 seems to be not > so ready to test mainline patches on. > > arch/riscv/include/asm/errata_list.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 4180312d2a70..605800bd390e 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \ > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > * 0000001 01001 rs1 000 00000 0001011 > * dcache.cva rs1 (clean, virtual address) > - * 0000001 00100 rs1 000 00000 0001011 > + * 0000001 00101 rs1 000 00000 0001011 > * > * dcache.cipa rs1 (clean then invalidate, physical address) > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \ > * 0000000 11001 00000 000 00000 0001011 > */ > #define THEAD_inval_A0 ".long 0x0265000b" > -#define THEAD_clean_A0 ".long 0x0245000b" > +#define THEAD_clean_A0 ".long 0x0255000b" the original encoding came from a chinese document from one of the t-head repos which only containted the original instruction as "dcache.cva" [0] ... so I guess some part was lost in translation :-) It's really great to see that the documentation improved a lot with that new repo with instruction encodings you mention in patch2. Using that new repo you mention, the change looks correct 0x4 -> 0x5 for the instruction selection, so Reviewed-by: Heiko Stuebner Though I'm on xmas vaction right now so can't test it on a board. Heiko [0] https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf page 233