* Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding [not found] <20221227020258.303900-1-uwu@icenowy.me> @ 2022-12-27 2:47 ` Guo Ren 2022-12-27 10:04 ` Icenowy Zheng 2022-12-30 22:12 ` Sergey Matyukevich 2022-12-27 10:31 ` Heiko Stuebner 1 sibling, 2 replies; 6+ messages in thread From: Guo Ren @ 2022-12-27 2:47 UTC (permalink / raw) To: Icenowy Zheng Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Heiko Stuebner, Nathan Chancellor, linux-riscv, linux-kernel Good catch. But I hope c906/910 can directly use paddr here. It's unnecessary to cause software translation & mmu translation here. diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b0add983530a..30650a0c4481 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -24,13 +24,13 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, switch (dir) { case DMA_TO_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, paddr, size, riscv_cbom_block_size); break; case DMA_FROM_DEVICE: - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(clean, vaddr, paddr, size, riscv_cbom_block_size); break; case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, paddr, size, riscv_cbom_block_size); break; default: break; @@ -47,7 +47,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, break; case DMA_FROM_DEVICE: case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, vaddr, paddr, size, riscv_cbom_block_size); break; default: break; @@ -57,8 +57,9 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); + phys_addr_t paddr = PFN_PHYS(page_to_pfn(x)); - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); + ALT_CMO_OP(flush, flush_addr, paddr, size, riscv_cbom_block_size); } On Tue, Dec 27, 2022 at 10:03 AM Icenowy Zheng <uwu@icenowy.me> wrote: > > The dcache.cva encoding shown in the comments are wrong, it's for > dcache.cval1 (which is restricted to L1) instead. > > Fix this in the comment and in the hardcoded instruction. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > --- > The code is tested on a LiteX SoC with OpenC906 core, and it > successfully boots to Systemd on a SD card connected to LiteSDCard. > > This change should be not noticable on C906, but on multi-core C910 > cluster it should fixes something. Unfortunately TH1520 seems to be not > so ready to test mainline patches on. > > arch/riscv/include/asm/errata_list.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 4180312d2a70..605800bd390e 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \ > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > * 0000001 01001 rs1 000 00000 0001011 > * dcache.cva rs1 (clean, virtual address) > - * 0000001 00100 rs1 000 00000 0001011 > + * 0000001 00101 rs1 000 00000 0001011 > * > * dcache.cipa rs1 (clean then invalidate, physical address) > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \ > * 0000000 11001 00000 000 00000 0001011 > */ > #define THEAD_inval_A0 ".long 0x0265000b" > -#define THEAD_clean_A0 ".long 0x0245000b" > +#define THEAD_clean_A0 ".long 0x0255000b" > #define THEAD_flush_A0 ".long 0x0275000b" > #define THEAD_SYNC_S ".long 0x0190000b" > > -- > 2.38.1 > -- Best Regards Guo Ren ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding 2022-12-27 2:47 ` [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Guo Ren @ 2022-12-27 10:04 ` Icenowy Zheng 2022-12-27 12:18 ` Conor Dooley 2022-12-30 22:12 ` Sergey Matyukevich 1 sibling, 1 reply; 6+ messages in thread From: Icenowy Zheng @ 2022-12-27 10:04 UTC (permalink / raw) To: Guo Ren Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Heiko Stuebner, Nathan Chancellor, linux-riscv, linux-kernel 在 2022-12-27星期二的 10:47 +0800，Guo Ren写道： > Good catch. But I hope c906/910 can directly use paddr here. It's > unnecessary to cause software translation & mmu translation here. This could be an enhancement independent of this patchset. In addition, I think this is some remaining of the design of the original patchset, in which adds Zicbom support and then Xtheadcmo support as some errata. > > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma- > noncoherent.c > index b0add983530a..30650a0c4481 100644 > --- a/arch/riscv/mm/dma-noncoherent.c > +++ b/arch/riscv/mm/dma-noncoherent.c > @@ -24,13 +24,13 @@ void arch_sync_dma_for_device(phys_addr_t paddr, > size_t size, > > switch (dir) { > case DMA_TO_DEVICE: > - ALT_CMO_OP(clean, vaddr, size, > riscv_cbom_block_size); > + ALT_CMO_OP(clean, vaddr, paddr, size, > riscv_cbom_block_size); Maybe the macro should be renamed as ALT_CMO_OP_VPA or similar thing, that means both VA and PA are provided and the most efficient one will be chosen, because CMO operations with PA is still some T-Head-only thing (Zicbom only supports VA). > break; > case DMA_FROM_DEVICE: > - ALT_CMO_OP(clean, vaddr, size, > riscv_cbom_block_size); > + ALT_CMO_OP(clean, vaddr, paddr, size, > riscv_cbom_block_size); > break; > case DMA_BIDIRECTIONAL: > - ALT_CMO_OP(flush, vaddr, size, > riscv_cbom_block_size); > + ALT_CMO_OP(flush, vaddr, paddr, size, > riscv_cbom_block_size); > break; > default: > break; > @@ -47,7 +47,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, > size_t size, > break; > case DMA_FROM_DEVICE: > case DMA_BIDIRECTIONAL: > - ALT_CMO_OP(flush, vaddr, size, > riscv_cbom_block_size); > + ALT_CMO_OP(flush, vaddr, paddr, size, > riscv_cbom_block_size); > break; > default: > break; > @@ -57,8 +57,9 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, > size_t size, > void arch_dma_prep_coherent(struct page *page, size_t size) > { > void *flush_addr = page_address(page); > + phys_addr_t paddr = PFN_PHYS(page_to_pfn(x)); > > - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); > + ALT_CMO_OP(flush, flush_addr, paddr, size, > riscv_cbom_block_size); > } > > On Tue, Dec 27, 2022 at 10:03 AM Icenowy Zheng <uwu@icenowy.me> > wrote: > > > > The dcache.cva encoding shown in the comments are wrong, it's for > > dcache.cval1 (which is restricted to L1) instead. > > > > Fix this in the comment and in the hardcoded instruction. > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > --- > > The code is tested on a LiteX SoC with OpenC906 core, and it > > successfully boots to Systemd on a SD card connected to LiteSDCard. > > > > This change should be not noticable on C906, but on multi-core C910 > > cluster it should fixes something. Unfortunately TH1520 seems to be > > not > > so ready to test mainline patches on. > > > > arch/riscv/include/asm/errata_list.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/errata_list.h > > b/arch/riscv/include/asm/errata_list.h > > index 4180312d2a70..605800bd390e 100644 > > --- a/arch/riscv/include/asm/errata_list.h > > +++ b/arch/riscv/include/asm/errata_list.h > > @@ -102,7 +102,7 @@ asm > > volatile(ALTERNATIVE( \ > > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > * 0000001 01001 rs1 000 00000 0001011 > > * dcache.cva rs1 (clean, virtual address) > > - * 0000001 00100 rs1 000 00000 0001011 > > + * 0000001 00101 rs1 000 00000 0001011 > > * > > * dcache.cipa rs1 (clean then invalidate, physical address) > > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > @@ -115,7 +115,7 @@ asm > > volatile(ALTERNATIVE( \ > > * 0000000 11001 00000 000 00000 0001011 > > */ > > #define THEAD_inval_A0 ".long 0x0265000b" > > -#define THEAD_clean_A0 ".long 0x0245000b" > > +#define THEAD_clean_A0 ".long 0x0255000b" > > #define THEAD_flush_A0 ".long 0x0275000b" > > #define THEAD_SYNC_S ".long 0x0190000b" > > > > -- > > 2.38.1 > > > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding 2022-12-27 10:04 ` Icenowy Zheng @ 2022-12-27 12:18 ` Conor Dooley 0 siblings, 0 replies; 6+ messages in thread From: Conor Dooley @ 2022-12-27 12:18 UTC (permalink / raw) To: Icenowy Zheng Cc: Guo Ren, Paul Walmsley, Palmer Dabbelt, Albert Ou, Heiko Stuebner, Nathan Chancellor, linux-riscv, linux-kernel [-- Attachment #1: Type: text/plain, Size: 170 bytes --] Hi Icenowy, I can't find this patch on lore or patchwork, (although the replies made it). Would you please resend it once the discussion has died down? Thanks, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding 2022-12-27 2:47 ` [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Guo Ren 2022-12-27 10:04 ` Icenowy Zheng @ 2022-12-30 22:12 ` Sergey Matyukevich 2022-12-31 4:36 ` Icenowy Zheng 1 sibling, 1 reply; 6+ messages in thread From: Sergey Matyukevich @ 2022-12-30 22:12 UTC (permalink / raw) To: Icenowy Zheng Cc: Guo Ren, Paul Walmsley, Palmer Dabbelt, Albert Ou, Heiko Stuebner, Nathan Chancellor, linux-riscv, linux-kernel > > The dcache.cva encoding shown in the comments are wrong, it's for > > dcache.cval1 (which is restricted to L1) instead. > > > > Fix this in the comment and in the hardcoded instruction. > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > --- > > The code is tested on a LiteX SoC with OpenC906 core, and it > > successfully boots to Systemd on a SD card connected to LiteSDCard. > > > > This change should be not noticable on C906, but on multi-core C910 > > cluster it should fixes something. Unfortunately TH1520 seems to be not > > so ready to test mainline patches on. > > > > arch/riscv/include/asm/errata_list.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > > index 4180312d2a70..605800bd390e 100644 > > --- a/arch/riscv/include/asm/errata_list.h > > +++ b/arch/riscv/include/asm/errata_list.h > > @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \ > > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > * 0000001 01001 rs1 000 00000 0001011 > > * dcache.cva rs1 (clean, virtual address) > > - * 0000001 00100 rs1 000 00000 0001011 > > + * 0000001 00101 rs1 000 00000 0001011 > > * > > * dcache.cipa rs1 (clean then invalidate, physical address) > > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \ > > * 0000000 11001 00000 000 00000 0001011 > > */ > > #define THEAD_inval_A0 ".long 0x0265000b" > > -#define THEAD_clean_A0 ".long 0x0245000b" > > +#define THEAD_clean_A0 ".long 0x0255000b" > > #define THEAD_flush_A0 ".long 0x0275000b" > > #define THEAD_SYNC_S ".long 0x0190000b" Nice catch ! I experimented with T-Head RVB-ICE board on the up-to-date upstream kernel, using device tree and some other bits from the vendor kernel [1]. Without this patch, emmc on this board does not work since noncoherent dma sync operations use incorrect 'clean' instruction. Applying this patch fixes emmc operations, so Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> [1] https://github.com/T-head-Semi/linux/tree/linux-5.10.4 Regards, Sergey ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding 2022-12-30 22:12 ` Sergey Matyukevich @ 2022-12-31 4:36 ` Icenowy Zheng 0 siblings, 0 replies; 6+ messages in thread From: Icenowy Zheng @ 2022-12-31 4:36 UTC (permalink / raw) To: Sergey Matyukevich Cc: Guo Ren, Paul Walmsley, Palmer Dabbelt, Albert Ou, Heiko Stuebner, Nathan Chancellor, linux-riscv, linux-kernel 在 2022-12-31星期六的 01:12 +0300，Sergey Matyukevich写道： > > > The dcache.cva encoding shown in the comments are wrong, it's for > > > dcache.cval1 (which is restricted to L1) instead. > > > > > > Fix this in the comment and in the hardcoded instruction. > > > > > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > > > --- > > > The code is tested on a LiteX SoC with OpenC906 core, and it > > > successfully boots to Systemd on a SD card connected to > > > LiteSDCard. > > > > > > This change should be not noticable on C906, but on multi-core > > > C910 > > > cluster it should fixes something. Unfortunately TH1520 seems to > > > be not > > > so ready to test mainline patches on. > > > > > > arch/riscv/include/asm/errata_list.h | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/riscv/include/asm/errata_list.h > > > b/arch/riscv/include/asm/errata_list.h > > > index 4180312d2a70..605800bd390e 100644 > > > --- a/arch/riscv/include/asm/errata_list.h > > > +++ b/arch/riscv/include/asm/errata_list.h > > > @@ -102,7 +102,7 @@ asm > > > volatile(ALTERNATIVE( \ > > > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > > * 0000001 01001 rs1 000 00000 0001011 > > > * dcache.cva rs1 (clean, virtual address) > > > - * 0000001 00100 rs1 000 00000 0001011 > > > + * 0000001 00101 rs1 000 00000 0001011 > > > * > > > * dcache.cipa rs1 (clean then invalidate, physical address) > > > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > > @@ -115,7 +115,7 @@ asm > > > volatile(ALTERNATIVE( \ > > > * 0000000 11001 00000 000 00000 0001011 > > > */ > > > #define THEAD_inval_A0 ".long 0x0265000b" > > > -#define THEAD_clean_A0 ".long 0x0245000b" > > > +#define THEAD_clean_A0 ".long 0x0255000b" > > > #define THEAD_flush_A0 ".long 0x0275000b" > > > #define THEAD_SYNC_S ".long 0x0190000b" > > Nice catch ! I experimented with T-Head RVB-ICE board on the up-to- > date > upstream kernel, using device tree and some other bits from the > vendor > kernel [1]. Without this patch, emmc on this board does not work > since > noncoherent dma sync operations use incorrect 'clean' instruction. > Applying this patch fixes emmc operations, so Thanks for testing on C910! I don't think this patch will make a significant difference on C906, so it's valuable! > > Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> > > [1] https://github.com/T-head-Semi/linux/tree/linux-5.10.4 > > Regards, > Sergey ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding [not found] <20221227020258.303900-1-uwu@icenowy.me> 2022-12-27 2:47 ` [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Guo Ren @ 2022-12-27 10:31 ` Heiko Stuebner 1 sibling, 0 replies; 6+ messages in thread From: Heiko Stuebner @ 2022-12-27 10:31 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren, Nathan Chancellor, Icenowy Zheng Cc: linux-riscv, linux-kernel, Icenowy Zheng Am Dienstag, 27. Dezember 2022, 03:02:57 CET schrieb Icenowy Zheng: > The dcache.cva encoding shown in the comments are wrong, it's for > dcache.cval1 (which is restricted to L1) instead. > > Fix this in the comment and in the hardcoded instruction. > > Signed-off-by: Icenowy Zheng <uwu@icenowy.me> > --- > The code is tested on a LiteX SoC with OpenC906 core, and it > successfully boots to Systemd on a SD card connected to LiteSDCard. > > This change should be not noticable on C906, but on multi-core C910 > cluster it should fixes something. Unfortunately TH1520 seems to be not > so ready to test mainline patches on. > > arch/riscv/include/asm/errata_list.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index 4180312d2a70..605800bd390e 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -102,7 +102,7 @@ asm volatile(ALTERNATIVE( \ > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > * 0000001 01001 rs1 000 00000 0001011 > * dcache.cva rs1 (clean, virtual address) > - * 0000001 00100 rs1 000 00000 0001011 > + * 0000001 00101 rs1 000 00000 0001011 > * > * dcache.cipa rs1 (clean then invalidate, physical address) > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > @@ -115,7 +115,7 @@ asm volatile(ALTERNATIVE( \ > * 0000000 11001 00000 000 00000 0001011 > */ > #define THEAD_inval_A0 ".long 0x0265000b" > -#define THEAD_clean_A0 ".long 0x0245000b" > +#define THEAD_clean_A0 ".long 0x0255000b" the original encoding came from a chinese document from one of the t-head repos which only containted the original instruction as "dcache.cva" [0] ... so I guess some part was lost in translation :-) It's really great to see that the documentation improved a lot with that new repo with instruction encodings you mention in patch2. Using that new repo you mention, the change looks correct 0x4 -> 0x5 for the instruction selection, so Reviewed-by: Heiko Stuebner <heiko@sntech.de> Though I'm on xmas vaction right now so can't test it on a board. Heiko [0] https://github.com/T-head-Semi/openc906/blob/main/doc/%E7%8E%84%E9%93%81C906%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf page 233 ^ permalink raw reply [flat|nested] 6+ messages in thread
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2022-12-27 2:47 ` [PATCH 1/2] riscv: errata: fix T-Head dcache.cva encoding Guo Ren
2022-12-27 10:04 ` Icenowy Zheng
2022-12-27 12:18 ` Conor Dooley
2022-12-30 22:12 ` Sergey Matyukevich
2022-12-31 4:36 ` Icenowy Zheng
2022-12-27 10:31 ` Heiko Stuebner
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