From: Anurup M <anurupvasu@gmail.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: dikshit.n@huawei.com, devicetree@vger.kernel.org,
wangkefeng.wang@huawei.com, sanil.kumar@hisilicon.com,
gabriele.paoloni@huawei.com, huangdaode@hisilicon.com,
tanxiaojun@huawei.com, john.garry@huawei.com,
will.deacon@arm.com, linux-kernel@vger.kernel.org,
xuwei5@hisilicon.com, linuxarm@huawei.com,
zhangshaokun@hisilicon.com, robh+dt@kernel.org,
anurup.m@huawei.com, shyju.pv@huawei.com,
linux-arm-kernel@lists.infradead.org, shiju.jose@huawei.com
Subject: Re: [PATCH v6 03/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
Date: Fri, 24 Mar 2017 15:48:55 +0530 [thread overview]
Message-ID: <58D4F28F.8080403@gmail.com> (raw)
In-Reply-To: <20170321172819.GE29116@leverpostej>
On Tuesday 21 March 2017 10:58 PM, Mark Rutland wrote:
> On Tue, Mar 21, 2017 at 02:07:42PM +0000, Mark Rutland wrote:
>> On Fri, Mar 10, 2017 at 01:27:27AM -0500, Anurup M wrote:
>>> +HiSilicon SoC chip is encapsulated by multiple CPU and IO dies. The CPU die
>>> +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
>>> +in HiP05/06/07 chips are further grouped as CPU clusters (CCL) which includes
>>> +4 cpu-cores each.
>>> +e.g. In the case of HiP05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
>>> +The L3 cache is further grouped as 4 L3 cache banks in a SCCL.
>>> +
>>> +The Hisilicon SoC PMU DT node bindings for uncore PMU devices are as below.
>>> +For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
>>> +the parent node will be the djtag node of the corresponding CPU die (SCCL).
>>> +
>>> +L3 cache
>>> +---------
>>> +The L3 cache is dedicated for each SCCL. Each SCCL in HiP05/06/07 chips have 4
>>> +L3 cache banks. Each L3 cache bank have separate DT nodes.
>>> +
>>> +Required properties:
>>> +
>>> + - compatible : This value should be as follows
>>> + (a) "hisilicon,hip05-pmu-l3c-v1" for v1 hw in HiP05 chipset
>>> + (b) "hisilicon,hip06-pmu-l3c-v1" for v1 hw in HiP06 chipset
>>> + (c) "hisilicon,hip07-pmu-l3c-v2" for v2 hw in HiP07 chipset
>>> +
>>> + - hisilicon,module-id : This property is a combination of two values
>>> + in the below order.
>>> + a) Module ID: The module identifier for djtag.
>>> + b) Instance or Bank ID: This will identify the L3 cache bank
>>> + or instance.
>> I take it this is intended two mean this property is two cells in
>> length, with one cell for each of the below.
>>
>> This is a somewhat confusing proeprty given that the name only applies
>> to the first half of the value...
> Please split this itno two properties, and have a hisilicon,instance-id
> for the L3 nodes.
Sure. Shall add hisilicon,instance-id for L3 nodes.
Thanks,
Anurup
> Thanks,
> Mark.
prev parent reply other threads:[~2017-03-24 10:19 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-10 6:27 [PATCH v6 03/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU Anurup M
2017-03-21 14:07 ` Mark Rutland
2017-03-21 17:28 ` Mark Rutland
2017-03-24 10:18 ` Anurup M [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=58D4F28F.8080403@gmail.com \
--to=anurupvasu@gmail.com \
--cc=anurup.m@huawei.com \
--cc=devicetree@vger.kernel.org \
--cc=dikshit.n@huawei.com \
--cc=gabriele.paoloni@huawei.com \
--cc=huangdaode@hisilicon.com \
--cc=john.garry@huawei.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxarm@huawei.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=sanil.kumar@hisilicon.com \
--cc=shiju.jose@huawei.com \
--cc=shyju.pv@huawei.com \
--cc=tanxiaojun@huawei.com \
--cc=wangkefeng.wang@huawei.com \
--cc=will.deacon@arm.com \
--cc=xuwei5@hisilicon.com \
--cc=zhangshaokun@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox