From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Florian Eckert <fe@dev.tdt.de>, Christian Lamparter <chunkeey@gmail.com>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs
Date: Tue, 07 Aug 2018 22:18:19 +0300 [thread overview]
Message-ID: <58c02aeff4285498272b0a13b8de2dc1282fded9.camel@linux.intel.com> (raw)
In-Reply-To: <37e92da47c20e8c771afcdb14c5532d8@dev.tdt.de>
On Tue, 2018-08-07 at 13:18 +0200, Florian Eckert wrote:
> Hello Andy
>
> I think this are the information you want to have.
>
I was rather asking for something like TRM.
By schematics, I meant a simplified GPIO buffers and pin control
explained on hardware level.
Below has nothing to do with either, unfortunately.
> On 2018-08-04 20:22, Christian Lamparter wrote:
> > As for the APUs. The vendor (PC Engines) happily provides
> > PDFs and schematics for their boards:
> > <https://www.pcengines.ch/pdf/apu1.pdf>
> > <https://www.pcengines.ch/schema/apu1c.pdf>
> > <https://www.pcengines.ch/pdf/apu2.pdf>
> > <http://pcengines.ch/schema/apu2c.pdf>
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
next prev parent reply other threads:[~2018-08-07 19:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-01 11:12 [PATCH] gpio: Add driver for PC Engines APU2/APU3 GPIOs Florian Eckert
2018-08-02 21:30 ` Linus Walleij
2018-08-03 16:08 ` Joe Perches
2018-08-04 18:22 ` Christian Lamparter
2018-08-07 11:18 ` Florian Eckert
2018-08-07 19:18 ` Andy Shevchenko [this message]
2018-08-03 19:08 ` Andy Shevchenko
2018-08-07 11:47 ` Florian Eckert
2018-08-24 10:56 ` Piotr Król
2018-08-30 5:54 ` Florian Eckert
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