From: Ethan Zhao <haifeng.zhao@linux.intel.com>
To: Zhou Shengqing <zhoushengqing@ttyinfo.com>
Cc: helgaas@kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, lkp@intel.com, llvm@lists.linux.dev,
oe-kbuild-all@lists.linux.dev
Subject: Re: [PATCH v4] PCI: Enable io space 1k granularity for intel cpu root port
Date: Fri, 26 Jul 2024 10:27:31 +0800 [thread overview]
Message-ID: <58ca7ae5-2197-4fd5-afe6-73743cd45e8c@linux.intel.com> (raw)
In-Reply-To: <20240725074403.12928-1-zhoushengqing@ttyinfo.com>
On 7/25/2024 3:44 PM, Zhou Shengqing wrote:
>> On 7/24/2024 2:35 PM, Zhou Shengqing wrote:
>>>>> Do you mean it shoud be like this?
>>>>>
>>>>> while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, 0x09a2, d))) {
>>>>> if (d->bus->number == dev->bus->number) {
>>>>> pci_read_config_word(d, 0x1c0, &en1k);
>>>>> if (en1k & 0x4) {
>>>>> pci_info(dev, "1K I/O windows enabled per %s EN1K setting\n", pci_name(d));
>>>>> dev->io_window_1k = 1;
>>>>> }
>>>>> }
>>>>> }
>>>>>
>>>>>> 00:00.0 System peripheral: Intel Corporation Device 09a2 (rev 20)
>>>>>> 00:0f.0 PCI bridge: Intel Corporation Device 1bbf (rev 10) (prog-if 00 [Normal decode])
>>>>>>
>>>>>>
>>>>>> 15:00.0 System peripheral: Intel Corporation Device 09a2 (rev 20)
>>>>>> 15:01.0 PCI bridge: Intel Corporation Device 352a (rev 04) (prog-if 00 [Normal decode])
>>>>>>
>>>>>> and if you check domain number only, they might sit on different bus, perhaps that
>>>>>> would make thing complex, could you make sure the VT-d is on the upstream bus of the
>>>>>> bridge ?
>>>>> I checked it on ICX SPR EMR GNR, VT-d is always on the same bus with root port,
>>>>> and VT-d device and function number is always 0.
>>>> Yes, every VT-d instance in the root complex and the root port integrated are
>>>> on the same bus. and VT-d is the first device of that bus.
>>>>
>>>> The EDS doesn't say if there is exception one of the VT-d instances in an
>>>> system its EN1K wasn't set while others were set, vice vesa. so I suggest
>>>> just check the VT-d and then set the root port's io_windows_1k of the same bus.
>>> But as Bjorn mentioned at July 12, 2024, 6:48 p.m.,
>>>
>>> "To be safe, "d" (the [8086:09a2] device) should be on the same bus as
>>> "dev" (with VMD, I think we get Root Ports *below* the VMD bridge,
>>> which would be a different bus, and they presumably are not influenced
>>> by the EN1K bit."
>>>
>>> When VMD enabled, just check bus number identical may lead to enable
>>> 1k io windows for VMD domain root port. E.g. 0000:80:00.0 is a
>>> VT-d(09a2). If VMD enabled, there might be a root port 10000:80:01.0 present.
>>> this code may lead to enable 10000:80:01.0 io_window_1k = 1.
>>> This is probably not expected.
>>>
>>> If I modify it like this,
>>>
>>> while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, 0x09a2, d))) {
>> BTW, don't save letters to use single letter variable 'd', please use 'vtd_dev' or
>> something else to express the VT-d device.
> Got it!
>
>>> ---if (d->bus->number == dev->bus->number) {
>>> +++if (d->bus == dev->bus) {
>> What if their 'bus' are NULL, though it is almost impossible. :)
>>
>>> pci_read_config_word(d, 0x1c0, &en1k);
>>> if (en1k & 0x4) {
>>> pci_info(dev, "1K I/O windows enabled per %s EN1K setting\n", pci_name(d));
>>> dev->io_window_1k = 1;
>>> }
>>> }
>>> }
>>>
>>> Can the situation mentioned above be avoided?
>> Yes, my understanding, as Bjorn pointed out root port extended from VMD
>> bridge not on the same bus as VT-d.
> For the root port extended from VMD, should the 1k window be set
> when BIOS setup EN1K knob enabled?
> In my case, I think EN1K should not apply to the VMD root port.
>
> But what I'm confused about is, how can I reasonably exclude the VMD root port
> in the code?
VMD, if enabled, is EP, not RP. and its RPs are mapped into its own space, and
sit at different buses as VT-d, no need to care about them if am correct.
Thanks,
Ethan
>>
>
next prev parent reply other threads:[~2024-07-26 2:27 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-21 2:06 [PATCH] PCI: Enable io space 1k granularity for intel cpu root port Zhou Shengqing
2024-06-21 21:02 ` Bjorn Helgaas
2024-06-22 15:06 ` zhoushengqing
2024-06-22 17:52 ` Bjorn Helgaas
2024-06-23 2:26 ` Zhou Shengqing
2024-06-24 8:01 ` Zhou Shengqing
2024-06-26 8:27 ` kernel test robot
2024-06-26 10:09 ` kernel test robot
2024-06-26 11:19 ` [PATCH v2] [PATCH v2] " Zhou Shengqing
2024-06-26 15:26 ` Bjorn Helgaas
2024-06-27 0:58 ` [PATCH v3] " Zhou Shengqing
2024-06-29 21:34 ` Bjorn Helgaas
2024-06-30 2:52 ` Re: [PATCH] " Zhou Shengqing
2024-07-01 21:06 ` Bjorn Helgaas
2024-07-02 3:56 ` [PATCH v4] Subject: " Zhou Shengqing
2024-07-12 18:48 ` Bjorn Helgaas
2024-07-23 8:04 ` Zhou Shengqing
2024-07-24 2:34 ` Ethan Zhao
2024-07-24 3:38 ` Zhou Shengqing
2024-07-24 5:39 ` Ethan Zhao
2024-07-24 6:35 ` [PATCH v4] " Zhou Shengqing
2024-07-24 7:51 ` Ethan Zhao
2024-07-25 7:44 ` Zhou Shengqing
2024-07-26 2:27 ` Ethan Zhao [this message]
2024-07-02 5:49 ` Re: Re: [PATCH] PCI: Enable io space 1k granularity for Zhou Shengqing
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