From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751928AbdECD3n (ORCPT ); Tue, 2 May 2017 23:29:43 -0400 Received: from mga02.intel.com ([134.134.136.20]:17304 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751382AbdECD3f (ORCPT ); Tue, 2 May 2017 23:29:35 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,282,1491289200"; d="scan'208";a="94873266" Message-ID: <59094E9D.6000103@intel.com> Date: Wed, 03 May 2017 11:29:33 +0800 From: "Shen, Xiaochen" User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: tglx@linutronix.de, linux-kernel@vger.kernel.org, x86@kernel.org CC: Fenghua Yu Subject: Re: [PATCH] x86/intel_rdt: Fix two typos in Documentation References: <1491498581-21735-1-git-send-email-xiaochen.shen@intel.com> In-Reply-To: <1491498581-21735-1-git-send-email-xiaochen.shen@intel.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Sorry, please ignore this patch. The first typo in this patch has been already fixed by: a9cad3d4f046 ("Documentation, x86: Intel Memory bandwidth allocation") A new patch is submitted to address the other typo left over: https://lkml.org/lkml/2017/5/2/595 Best regards Xiaochen Shen On 2017/4/7 1:09, Xiaochen Shen wrote: > Both typos are in example 3. > > Because cache id 0 is the only cache id, the ";" is redundant in > "# echo "L3:0=ffc00;" > p0/schemata". > > And "C0" in "# echo C0 > p0/cpus" is wrong because it specifies core > 6-7 instead of wanted core 4-7. > > Correct the typos to avoid confusion. > > Signed-off-by: Xiaochen Shen > Signed-off-by: Fenghua Yu > --- > Documentation/x86/intel_rdt_ui.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt > index 51cf6fa..cd752c1 100644 > --- a/Documentation/x86/intel_rdt_ui.txt > +++ b/Documentation/x86/intel_rdt_ui.txt > @@ -206,12 +206,12 @@ Next we make a resource group for our real time cores and give > it access to the "top" 50% of the cache on socket 0. > > # mkdir p0 > -# echo "L3:0=ffc00;" > p0/schemata > +# echo "L3:0=ffc00" > p0/schemata > > Finally we move core 4-7 over to the new group and make sure that the > kernel and the tasks running there get 50% of the cache. > > -# echo C0 > p0/cpus > +# echo F0 > p0/cpus > > 4) Locking between applications >