Re: [PATCH 0/4] clk: thead: Misc changes to TH1520 clock driver

[Icenowy Zheng <uwu@icenowy.me>]

在 2025-08-12星期二的 09:24 -0700，Drew Fustini写道：
> On Tue, Aug 12, 2025 at 09:42:23PM +0800, Icenowy Zheng wrote:
> > 在 2025-08-12星期二的 13:42 +0800，Icenowy Zheng写道：
> > > This patchset is my changes to the TH1520 clock driver, mainly
> > > for
> > > supporting the display controller (the first 3).
> > > 
> > > The first two are functionality additions, with the first one
> > > adding
> > > support for enabling/disabling PLLs (for DPU PLL) and the second
> > > one
> > > adding support for changing DPU dividers.
> > > 
> > > The 3rd one is to address hang issues met when testing the DPU
> > > driver
> > > w/o clk_ignore_unused command line option.
> > > 
> > > The 4th one has no relationship to display, and only exists for
> > > my
> > > need
> > > to change an arbitrary GPIO (well, GPIO3_3, the one controlling
> > > the
> > > fan
> > > on Lichee Pi 4A) with gpioset.
> > > 
> > > This patchset has a dependency (a 0th one) [1].
> > > 
> > > [1]
> > > https://lore.kernel.org/linux-riscv/20250809-fix_clocks_thead_aug_9-v1-1-299c33d7a593@samsung.com/
> > > 
> > 
> > Oops, looks like this patchset deserves a new revision now...
> 
> Thanks, that does make it easier to apply with 'b4 shazam'.
> 
> > PATCH 2/4 has a round_rate() implementation, which is considered
> > out-
> > of-date and determine_rate() will replace it.
> 
> I saw your reply over in the big patchset from Brian Masney. That's
> good
> that we will be able to skip adding round_rate() to the driver.
> 
> > PATCH 3/4 was broken during rebasing.
> > 
> > PATCH 4/4 is found to be not working (and even makes padctrl0 an
> > orphan
> > clock). Yao Zi told me that I need to first do some changes to
> > ccu_gate
> > code.
> 
> Is there a way to test the functionality without additional patches
> from
> your branch?

To be honest I know about little...

The 4th patch is the only one easy to test, but it's broken... (A
refactor must come with it to make it work).

For patch 1~3, if you are brave enough, in file drivers/clk/clk.c,
change the line `#undef CLOCK_ALLOW_WRITE_DEBUGFS` 's `#undef` to
`#define` may give you some testing facility in debugfs -- writing some
clock rate (e.g. 148500000) to /sys/kernel/debug/clk/dpu1-
pixelclk/clk_rate and then 1 to /sys/kernel/debug/clk/dpu1-
pixelclk/clk_prepare_enable in this situation could mimic what the DC
driver does -- I believe in /sys/kernel/debug/clk/clk_summary the
effect can be shown (dpu1-pll hardware enable becomes Y and dpu1-
pixelclk shows the expected rate.

WARNING: THE PARAGRAPH ABOVE IS ONLY BASED ON MY READING OF CODE, NOT
VERIFIED, CAN GET A DRAGON TO BURN YOUR HOUSE.

> 
> I look forward to v2. Thanks for working on the display. 
> 
> -Drew