From: "Heiko Stübner" <heiko@sntech.de>
To: James Hogan <james.hogan@imgtec.com>
Cc: Mike Turquette <mturquette@linaro.org>,
linux-metag@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>
Subject: Re: [PATCH 15/15] metag: tz1090: add TZ1090 clocks to device tree
Date: Tue, 25 Nov 2014 00:03:43 +0100 [thread overview]
Message-ID: <5932816.ccTTaBqqIv@diego> (raw)
In-Reply-To: <20141121100647.GF12456@jhogan-linux.le.imgtec.org>
Am Freitag, 21. November 2014, 10:06:47 schrieb James Hogan:
> On Thu, Nov 20, 2014 at 01:56:24PM +0100, Heiko Stübner wrote:
> > I don't know enough about your clock structure, but it looks quite a bit
> > like Mike's mail from May [0] may apply here too.
> >
> > The register layout also suggests that it is indeed one clock ip-block:
> >
> > 0x02005908 0x4 CR_TOP_CLKSWITCH
> > 0x0200590c 0x4 CR_TOP_CLKENAB
> > 0x02005950 0x4 CR_TOP_SYSPLL_CTL0
> > 0x02005954 0x4 CR_TOP_SYSPLL_CTL1
> > 0x02005988 0x4 CR_TOP_CLKSWITCH2
> > 0x0200598c 0x4 CR_TOP_CLKENAB2
> > ...
> >
> >
> > [0] https://lkml.org/lkml/2014/5/14/715
>
> Thanks, that does make sense. It's probably more like 4 memory regions
> ("top" level, "perip" peripheral registers, "hep" high end peripheral
> registers, and "pdc" powerdown controller registers), but it could
> certainly still have a single binding with multiple memory regions to
> simplify the clock specifiers.
It could also make sense to have 4 clock controller nodes for those. I guess
it all depends on how the hardware is layed out.
For example on Rockchip SoCs, all of this is contained in the "APB CRU" (Clock
and Reset Unit) with a memory region of <0x20000000 0x4000> - so here one
hardware-block that contains all the clocks and also the reset controller.
On the other hand it might very well be more than one ip-block on your
platform.
So I guess it comes down to looking at the memory map [or documentation :-) ]
to determine how many ip blocks there really are.
Heiko
next prev parent reply other threads:[~2014-11-24 23:00 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-19 23:15 [PATCH 00/15] tz1090: add clock components James Hogan
2014-11-19 23:15 ` [PATCH 01/15] clk: divider: replace bitfield width with mask James Hogan
2014-11-20 11:19 ` Tero Kristo
2014-11-20 11:59 ` James Hogan
2014-11-19 23:15 ` [PATCH 02/15] clk: divider: expose new clk_register_divider_mask James Hogan
2014-11-19 23:15 ` [PATCH 03/15] dt: binding: add binding for tz1090-pll clock James Hogan
2014-11-19 23:15 ` [PATCH 04/15] clk: tz1090: add PLL clock driver James Hogan
2014-11-19 23:15 ` [PATCH 05/15] dt: binding: add binding for TZ1090 gate bank James Hogan
2014-11-19 23:15 ` [PATCH 06/15] clk: tz1090: add gate bank clock driver James Hogan
2014-11-19 23:15 ` [PATCH 07/15] dt: binding: add binding for TZ1090 mux bank James Hogan
2014-11-19 23:15 ` [PATCH 08/15] clk: tz1090: add mux bank clock driver James Hogan
2014-11-19 23:15 ` [PATCH 09/15] dt: binding: add binding for TZ1090 clock deleter James Hogan
2014-11-19 23:15 ` [PATCH 10/15] clk: tz1090: add deleter clock driver James Hogan
2014-11-19 23:15 ` [PATCH 11/15] dt: binding: add binding for TZ1090 PDC clock James Hogan
2014-11-19 23:15 ` [PATCH 12/15] clk: tz1090: add PDC clock driver James Hogan
2014-11-19 23:15 ` [PATCH 13/15] dt: binding: add binding for TZ1090 divider clock James Hogan
2014-11-19 23:15 ` [PATCH 14/15] clk: tz1090: add divider clock driver James Hogan
2014-11-19 23:15 ` [PATCH 15/15] metag: tz1090: add TZ1090 clocks to device tree James Hogan
2014-11-20 12:56 ` Heiko Stübner
2014-11-21 10:06 ` James Hogan
2014-11-24 23:03 ` Heiko Stübner [this message]
2014-11-25 11:39 ` James Hogan
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