From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47D0721255D; Fri, 22 Aug 2025 11:12:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755861128; cv=none; b=cgM0RyYPMV+E7RLlwfJQiJM8aFvFeuhxDB5hQT0Kb3Ap+GQjIPtgiUeZIBsaEzPozeNp7mLO+yIS5SOfZIT1nuU29Kh1ejxdDvVC3GpDC5MxMJwfZxwXS5UcvQZAyVBMTkXcYqnD5mh5pkWl51AN6eEVnDeX/OeMbfv4Ne3aHaU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755861128; c=relaxed/simple; bh=N8II0tKKmr+jYcX2kJ5FQ3s6Z9IvUZ67ogJraYwkwok=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Nakl5cbR9BQBt+NxkTgWw+WaPRaVUiAp1o6hVcOJP9X8wausKgeGt8X0nT/FWKLCm5ZwQqwlKvL7GQ7jDmSwx8oD5HPs3kEnct/LBYHTQlkes7qcq5JuzV8AurFUtcMlAANoAvUIBhSsEvSvW+vbhfgYgbwEHlvy7gSyGzCnvdE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T2Ib62DD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T2Ib62DD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B5024C4CEED; Fri, 22 Aug 2025 11:12:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755861128; bh=N8II0tKKmr+jYcX2kJ5FQ3s6Z9IvUZ67ogJraYwkwok=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=T2Ib62DDl42DK3INX+lvLhkuJhI2GerHhn03pcnvfWvOa3dJkj4JPa/AesfThZXBx p7aJddQhoLLE/ZBgDDebC7CZ7gb8Sq/w5xiXmAnXt/m81BF0oy40umPD6q9P1TGeYi 0zPOAbH2v1A3Zeevh5rWSUKJ7X6eXGZRKyBvAW3AMcSiKnnJ0lC/ueQbHKAdmZXAge frp2a0fw7zS9JNAui+cD7X76jHJMIKX8xr99meyrWCzvJ8fo3k/WNmK1fA+MtyyznU kRwJRbHoBYtluoXDlsKPYtUybXloqlaoS7/vvEKAlhCMsxh+Q6E7l/rflNovf2cSUs kBYBc4hVWNnxg== Message-ID: <5950bff3-cce5-4a26-aad7-9314542f70dd@kernel.org> Date: Fri, 22 Aug 2025 13:12:01 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8ULP compatible string To: Guoniu Zhou , Rui Miguel Silva , Laurent Pinchart , Martin Kepplinger , Purism Kernel Team , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Philipp Zabel , Frank Li Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250822-csi2_imx8ulp-v2-0-26a444394965@nxp.com> <20250822-csi2_imx8ulp-v2-1-26a444394965@nxp.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 22/08/2025 12:50, Guoniu Zhou wrote: > The CSI-2 receiver in the i.MX8ULP is almost identical to the version > present in the i.MX8QXP/QM. But have different reset and clock design, > so add a device-specific compatible string for i.MX8ULP to handle the > difference. > > Signed-off-by: Guoniu Zhou > --- > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 42 ++++++++++++++++++++-- > 1 file changed, 40 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > index 3389bab266a9adbda313c8ad795b998641df12f3..ca485d1d596c274eb7e1f3cdc39c61bb54cc0685 100644 > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > @@ -21,7 +21,9 @@ properties: > - fsl,imx8mq-mipi-csi2 > - fsl,imx8qxp-mipi-csi2 > - items: > - - const: fsl,imx8qm-mipi-csi2 > + - enum: > + - fsl,imx8ulp-mipi-csi2 > + - fsl,imx8qm-mipi-csi2 That;s some sort of random change. Previously code was correctly sorted - u > q... now it is not > - const: fsl,imx8qxp-mipi-csi2 > > reg: > @@ -39,12 +41,19 @@ properties: > clock that the RX DPHY receives. > - description: ui is the pixel clock (phy_ref up to 333Mhz). > See the reference manual for details. > + - description: pclk is the lpav bus clock of i.MX8ULP. It provides > + clock to CSI_REG module. > + (see section "4.5.4 Peripheral clock diagrams, > + Figure 76 MIPI CSI clocking" in IMX8ULPRM REV1) > + minItems: 3 > > clock-names: > items: > - const: core > - const: esc > - const: ui > + - const: pclk > + minItems: 3 > > power-domains: > maxItems: 1 > @@ -125,19 +134,48 @@ required: > - ports > > allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8ulp-mipi-csi2 > + then: > + properties: > + reg: > + minItems: 2 > + resets: > + maxItems: 2 > + minItems: 2 minItems goes before max. > + clocks: > + minItems: 4 > + clock-names: > + minItems: 4 > + > - if: > properties: > compatible: > contains: > enum: > - fsl,imx8qxp-mipi-csi2 > + not: > + contains: > + enum: > + - fsl,imx8ulp-mipi-csi2 > then: > properties: > reg: > minItems: 2 > resets: > maxItems: 1 > - else: > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8mq-mipi-csi2 > + then: > properties: > reg: > maxItems: 1 I don't see what we asked you for - restrict other variants. Answer previous review: "Or explain why old hardware has now 4 clocks. That explanation is missing." > Best regards, Krzysztof