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bh=aWPAionUGYVqkBpz5QQVAcYUIfxJMKwBFtRZhqGCqzM=; b=RuiFb+t17z7NWutMYXVwxR3XZl8vkhaNc+HPwldTvIxBW6iyroeFZlOxk4gQPyZXwMi0q/fFm32VS+2LnzuALx0/ZKwHfOe9HNXwL90TgwrZWwMkyhSkYRdbeL6qDnv6SPMU1W/6wcWNx61Y9DdZXz68YT2tF0eO1hrTkhFQfAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1767599726; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type:Message-Id:Reply-To; bh=aWPAionUGYVqkBpz5QQVAcYUIfxJMKwBFtRZhqGCqzM=; b=dejfNqMo6xmOUjexvSDcHRAdx7eGKVoKzOgsSAouO/QpFOaFtb/2l++R+0lz/IIE GA1s1tqndtY+CqwFmV4yoqxwS+YAzplmyPeZ88imwA/+zgkAwGVoPqWSMcSAHKcC4t9 g3QSRCI3m5/DeUkzc8rpw6Q/Z4h7E5iLJDvEHf7w= Received: by mx.zohomail.com with SMTPS id 1767599722778915.547246258709; Sun, 4 Jan 2026 23:55:22 -0800 (PST) From: Nicolas Frattaroli To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Chaoyi Chen , Kever Yang , Sebastian Reichel , Cristian Ciocaltea , Frank Wang , Alexey Charkov , Liang Chen , Finley Xiao , Elaine Zhang , Yifeng Zhao , Chaoyi Chen Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: rockchip: Fix wrong register range of rk3576 gpu Date: Mon, 05 Jan 2026 08:55:17 +0100 Message-ID: <5954009.DvuYhMxLoT@workhorse> In-Reply-To: <20251230090246.46-1-kernel@airkyi.com> References: <20251230090246.46-1-kernel@airkyi.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="utf-8" On Tuesday, 30 December 2025 10:02:46 Central European Standard Time Chaoyi Chen wrote: > From: Chaoyi Chen > > According to RK3576 TRM part1 page13, the size of the GPU registers > is 128 KB. > > Fixes: 57b1ce903966 ("arm64: dts: rockchip: Add rk3576 SoC base DT") > Signed-off-by: Chaoyi Chen > --- > arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > index 6284e7bdc442..b375015f0662 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > @@ -1271,7 +1271,7 @@ power-domain@RK3576_PD_VO1 { > > gpu: gpu@27800000 { > compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; > - reg = <0x0 0x27800000 0x0 0x200000>; > + reg = <0x0 0x27800000 0x0 0x20000>; > assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; > assigned-clock-rates = <198000000>; > clocks = <&cru CLK_GPU>; > This is only true if you only consider the GPU_CONTROL and JOB_CONTROL register ranges, and leave out the MMU_STAGE1 and MMU_STAGE2 ranges. I don't know if those need to be mapped, since the MMU control registers are < 0x2000. What do other bifrost devices do? Kind regards, Nicolas Frattaroli