[PATCH v4 4/5] ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi

[PATCH v4 4/5] ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi

[Doug Anderson]

The EHCI and HSIC device tree nodes were added in the wrong place.
Fix them.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v4:
- Based on the proper patch

Changes in v3:
- EHCI and HSIC move new for version 3.

 arch/arm/boot/dts/rk3288.dtsi | 41 ++++++++++++++++++++---------------------
 1 file changed, 20 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 9713054..49c99f2 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -156,6 +156,17 @@
 		status = "disabled";
 	};
 
+	usb_host0_ehci: usb@ff500000 {
+		compatible = "generic-ehci";
+		reg = <0xff500000 0x100>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_USBHOST0>;
+		clock-names = "usbhost";
+		status = "disabled";
+	};
+
+	/* NOTE: ohci@ff520000 doesn't actually work on hardware */
+
 	usb_host1: usb@ff540000 {
 		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 				"snps,dwc2";
@@ -176,6 +187,15 @@
 		status = "disabled";
 	};
 
+	usb_hsic: usb@ff5c0000 {
+		compatible = "generic-ehci";
+		reg = <0xff5c0000 0x100>;
+		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HSIC>;
+		clock-names = "usbhost";
+		status = "disabled";
+	};
+
 	uart2: serial@ff690000 {
 		compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 		reg = <0xff690000 0x100>;
@@ -270,27 +290,6 @@
 		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 	};
-
-	usb_host0_ehci: usb@ff500000 {
-		compatible = "generic-ehci";
-		reg = <0xff500000 0x100>;
-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_USBHOST0>;
-		clock-names = "usbhost";
-		status = "disabled";
-	};
-
-	/* NOTE: ohci@ff520000 doesn't actually work on hardware */
-
-	usb_hsic: usb@ff5c0000 {
-		compatible = "generic-ehci";
-		reg = <0xff5c0000 0x100>;
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_HSIC>;
-		clock-names = "usbhost";
-		status = "disabled";
-	};
-
 	gic: interrupt-controller@ffc01000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
-- 
2.0.0.526.g5318336

Re: [PATCH v4 4/5] ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi

[Heiko Stübner]

Am Donnerstag, 31. Juli 2014, 15:49:35 schrieb Doug Anderson:
> The EHCI and HSIC device tree nodes were added in the wrong place.
> Fix them.
> 
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

hmm, not sure if this counts as fix ... aka material for 3.17-rc2 or should 
wait for 3.18. Simply because it's more a cosmetic thing.

If it is a fix, could base it on the appropriate dts revision, because here 
it's in the middle of the dwc2 series, including the
	usb_host1: usb@ff540000
nodes.


Heiko

> ---
> Changes in v4:
> - Based on the proper patch
> 
> Changes in v3:
> - EHCI and HSIC move new for version 3.
> 
>  arch/arm/boot/dts/rk3288.dtsi | 41
> ++++++++++++++++++++--------------------- 1 file changed, 20 insertions(+),
> 21 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 9713054..49c99f2 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -156,6 +156,17 @@
>  		status = "disabled";
>  	};
> 
> +	usb_host0_ehci: usb@ff500000 {
> +		compatible = "generic-ehci";
> +		reg = <0xff500000 0x100>;
> +		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_USBHOST0>;
> +		clock-names = "usbhost";
> +		status = "disabled";
> +	};
> +
> +	/* NOTE: ohci@ff520000 doesn't actually work on hardware */
> +
>  	usb_host1: usb@ff540000 {
>  		compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
>  				"snps,dwc2";
> @@ -176,6 +187,15 @@
>  		status = "disabled";
>  	};
> 
> +	usb_hsic: usb@ff5c0000 {
> +		compatible = "generic-ehci";
> +		reg = <0xff5c0000 0x100>;
> +		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_HSIC>;
> +		clock-names = "usbhost";
> +		status = "disabled";
> +	};
> +
>  	uart2: serial@ff690000 {
>  		compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
>  		reg = <0xff690000 0x100>;
> @@ -270,27 +290,6 @@
>  		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
>  		status = "disabled";
>  	};
> -
> -	usb_host0_ehci: usb@ff500000 {
> -		compatible = "generic-ehci";
> -		reg = <0xff500000 0x100>;
> -		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&cru HCLK_USBHOST0>;
> -		clock-names = "usbhost";
> -		status = "disabled";
> -	};
> -
> -	/* NOTE: ohci@ff520000 doesn't actually work on hardware */
> -
> -	usb_hsic: usb@ff5c0000 {
> -		compatible = "generic-ehci";
> -		reg = <0xff5c0000 0x100>;
> -		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&cru HCLK_HSIC>;
> -		clock-names = "usbhost";
> -		status = "disabled";
> -	};
> -
>  	gic: interrupt-controller@ffc01000 {
>  		compatible = "arm,gic-400";
>  		interrupt-controller;

Re: [PATCH v4 4/5] ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi

[Doug Anderson]

Heiko,

On Fri, Aug 1, 2014 at 2:17 AM, Heiko Stübner <heiko@sntech.de> wrote:
> Am Donnerstag, 31. Juli 2014, 15:49:35 schrieb Doug Anderson:
>> The EHCI and HSIC device tree nodes were added in the wrong place.
>> Fix them.
>>
>> Signed-off-by: Doug Anderson <dianders@chromium.org>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>
> hmm, not sure if this counts as fix ... aka material for 3.17-rc2 or should
> wait for 3.18. Simply because it's more a cosmetic thing.
>
> If it is a fix, could base it on the appropriate dts revision, because here
> it's in the middle of the dwc2 series, including the
>         usb_host1: usb@ff540000
> nodes.

It didn't seem too urgent since it's just cosmetic.  ...but I didn't
want to send up my fixup and then cause an immediate conflict with
Kever.  :(  ...that's why I asked him to just include it in his
series.

If you want me to spin this patch separately (and then Kever can spin
his), let me know.  I know that for me Kever's series was still not
making the dwc2 controller work 100% correctly for me (so maybe he'll
need to spin anyway?), but someone else at work had it working so
something is fishy.  Unfortunately I'm away from my computer and board
for the next several days, so it might be a while before I can
investigate more...

-Doug