Re: [PATCH v5 1/3] phy: rockchip: inno-usb2: convert clock management to bulk

Heiko Stübner
2024-10-15T06:18:40Z

Am Freitag, 11. Oktober 2024, 08:51:38 CEST schrieb Frank Wang:
> From: Frank Wang <frank.wang@rock-chips.com>
>
> Since some Rockchip SoCs (e.g RK3576) have more than one clock,
> this converts the clock management from single to bulk method to
> make the driver more flexible.
>
> Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

thanks a lot for all the work you did on this

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
> Changelog:
> V5:
> - use dev_err_probe() in clock enable error path in probe.
>
> v4:
> - a new patch split from the [PATCH v3 2/2], suggestions from Heiko.
>
> v1-v3:
> - none
>
> drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 45 +++++++++++++++----
> 1 file changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> index 6e5214862b8a3..f71266c27091e 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> @@ -229,9 +229,10 @@ struct rockchip_usb2phy_port {
> * @dev: pointer to device.
> * @grf: General Register Files regmap.
> * @usbgrf: USB General Register Files regmap.
> - * @clk: clock struct of phy input clk.
> + * @clks: array of phy input clocks.
> * @clk480m: clock struct of phy output clk.
> * @clk480m_hw: clock struct of phy output clk management.
> + * @num_clks: number of phy input clocks.
> * @phy_reset: phy reset control.
> * @chg_state: states involved in USB charger detection.
> * @chg_type: USB charger types.
> @@ -246,9 +247,10 @@ struct rockchip_usb2phy {
> struct device *dev;
> struct regmap *grf;
> struct regmap *usbgrf;
> - struct clk *clk;
> + struct clk_bulk_data *clks;
> struct clk *clk480m;
> struct clk_hw clk480m_hw;
> + int num_clks;
> struct reset_control *phy_reset;
> enum usb_chg_state chg_state;
> enum power_supply_type chg_type;
> @@ -310,6 +312,13 @@ static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
> return 0;
> }
>
> +static void rockchip_usb2phy_clk_bulk_disable(void *data)
> +{
> + struct rockchip_usb2phy *rphy = data;
> +
> + clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
> +}
> +
> static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
> {
> struct rockchip_usb2phy *rphy =
> @@ -376,7 +385,9 @@ rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
> {
> struct device_node *node = rphy->dev->of_node;
> struct clk_init_data init;
> + struct clk *refclk = NULL;
> const char *clk_name;
> + int i;
> int ret = 0;
>
> init.flags = 0;
> @@ -386,8 +397,15 @@ rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
> /* optional override of the clockname */
> of_property_read_string(node, "clock-output-names", &init.name);
>
> - if (rphy->clk) {
> - clk_name = __clk_get_name(rphy->clk);
> + for (i = 0; i < rphy->num_clks; i++) {
> + if (!strncmp(rphy->clks[i].id, "phyclk", 6)) {
> + refclk = rphy->clks[i].clk;
> + break;
> + }
> + }
> +
> + if (!IS_ERR(refclk)) {
> + clk_name = __clk_get_name(refclk);
> init.parent_names = &clk_name;
> init.num_parents = 1;
> } else {
> @@ -1399,15 +1417,26 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev)
> if (IS_ERR(rphy->phy_reset))
> return PTR_ERR(rphy->phy_reset);
>
> - rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk");
> - if (IS_ERR(rphy->clk))
> - return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk),
> - "failed to get phyclk\n");
> + ret = devm_clk_bulk_get_all(dev, &rphy->clks);
> + if (ret == -EPROBE_DEFER)
> + return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
> + "failed to get phy clock\n");
> +
> + /* Clocks are optional */
> + rphy->num_clks = ret < 0 ? 0 : ret;
>
> ret = rockchip_usb2phy_clk480m_register(rphy);
> if (ret)
> return dev_err_probe(dev, ret, "failed to register 480m output clock\n");
>
> + ret = clk_bulk_prepare_enable(rphy->num_clks, rphy->clks);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to enable phy clock\n");
> +
> + ret = devm_add_action_or_reset(dev, rockchip_usb2phy_clk_bulk_disable, rphy);
> + if (ret)
> + return ret;
> +
> if (rphy->phy_cfg->phy_tuning) {
> ret = rphy->phy_cfg->phy_tuning(rphy);
> if (ret)
>