From: Wei Wang <wei.w.wang@intel.com>
To: Jim Mattson <jmattson@google.com>, Andi Kleen <ak@linux.intel.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
"kvm list" <kvm@vger.kernel.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Kan Liang" <kan.liang@intel.com>,
"Ingo Molnar" <mingo@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>,
like.xu@intel.com, "Jann Horn" <jannh@google.com>,
arei.gonglei@huawei.com
Subject: Re: [PATCH v4 05/10] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest
Date: Tue, 08 Jan 2019 15:53:49 +0800 [thread overview]
Message-ID: <5C34570D.6010208@intel.com> (raw)
In-Reply-To: <CALMp9eT2J=qFTEEpsym_aqeCRwyCquTYnY8=taZ3nY3rs8WeJA@mail.gmail.com>
On 01/08/2019 02:48 AM, Jim Mattson wrote:
> On Mon, Jan 7, 2019 at 10:20 AM Andi Kleen <ak@linux.intel.com> wrote:
>>> The issue is compatibility. Prior to your change, reading this MSR
>>> from a VM would raise #GP. After your change, it won't. That means
>>> that if you have a VM migrating between hosts with kernel versions
>>> before and after this change, the results will be inconsistent. In the
>> No it will not be. All Linux kernel uses of this MSR are guarded
>> by a CPUID check.
> Linux usage is irrelevant to the architected behavior of the virtual
> CPU. According to volume 4 of the SDM, this MSR is only supported when
> CPUID.01H:ECX.PDCM [bit 15] is set. Therefore, kvm should raise #GP
> whenever a guest tries to read this MSR and the guest's
> CPUID.01H:ECX.PDCM [bit 15] is clear.
>
Probably one more check would be better:
if (!boot_cpu_has(X86_FEATURE_PDCM) ||
!guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
return 1;
(host isn't expected to read this MSR when PDCM is not supported
by the guest, so don't have "!msr_info->host_initiate" added to above)
Best,
Wei
next prev parent reply other threads:[~2019-01-08 7:48 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-26 9:25 [PATCH v4 00/10] Guest LBR Enabling Wei Wang
2018-12-26 9:25 ` [PATCH v4 01/10] perf/x86: fix the variable type of the LBR MSRs Wei Wang
2018-12-26 9:25 ` [PATCH v4 02/10] perf/x86: add a function to get the lbr stack Wei Wang
2018-12-26 9:25 ` [PATCH v4 03/10] KVM/x86: KVM_CAP_X86_GUEST_LBR Wei Wang
2018-12-26 9:25 ` [PATCH v4 04/10] KVM/x86: intel_pmu_lbr_enable Wei Wang
2019-01-02 16:33 ` Liang, Kan
2019-01-04 9:58 ` Wei Wang
2019-01-04 15:57 ` Liang, Kan
2019-01-05 10:09 ` Wei Wang
2019-01-07 14:22 ` Liang, Kan
2019-01-08 6:13 ` Wei Wang
2019-01-08 14:08 ` Liang, Kan
2019-01-09 1:54 ` Wei Wang
2019-01-02 23:26 ` Jim Mattson
2019-01-03 7:22 ` Wei Wang
2019-01-03 15:34 ` Jim Mattson
2019-01-03 17:18 ` Andi Kleen
2019-01-04 10:09 ` Wei Wang
2019-01-04 15:53 ` Jim Mattson
2019-01-05 10:15 ` Wang, Wei W
2018-12-26 9:25 ` [PATCH v4 05/10] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest Wei Wang
2019-01-02 23:40 ` Jim Mattson
2019-01-03 8:00 ` Wei Wang
2019-01-03 15:25 ` Jim Mattson
2019-01-07 9:15 ` Wei Wang
2019-01-07 18:05 ` Jim Mattson
2019-01-07 18:20 ` Andi Kleen
2019-01-07 18:48 ` Jim Mattson
2019-01-07 20:14 ` Andi Kleen
2019-01-07 21:00 ` Jim Mattson
2019-01-08 7:53 ` Wei Wang [this message]
2019-01-08 17:19 ` Jim Mattson
2018-12-26 9:25 ` [PATCH v4 06/10] perf/x86: no counter allocation support Wei Wang
2018-12-26 9:25 ` [PATCH v4 07/10] KVM/x86/vPMU: Add APIs to support host save/restore the guest lbr stack Wei Wang
2018-12-26 9:25 ` [PATCH v4 08/10] perf/x86: save/restore LBR_SELECT on vCPU switching Wei Wang
2018-12-26 9:25 ` [PATCH v4 09/10] perf/x86: function to check lbr user callstack mode Wei Wang
2018-12-26 9:25 ` [PATCH v4 10/10] KVM/x86/lbr: lazy save the guest lbr stack Wei Wang
2018-12-27 20:51 ` Andi Kleen
2018-12-28 3:47 ` Wei Wang
2018-12-28 19:10 ` Andi Kleen
2018-12-27 20:52 ` [PATCH v4 10/10] KVM/x86/lbr: lazy save the guest lbr stack II Andi Kleen
2018-12-29 4:25 ` Wang, Wei W
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