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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id c21sm7058420wre.35.2019.03.16.07.35.09 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 16 Mar 2019 07:35:10 -0700 (PDT) Message-ID: <5C8D099D.5020206@baylibre.com> Date: Sat, 16 Mar 2019 15:35:09 +0100 From: Neil Armstrong User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: Martin Blumenstingl CC: khilman@baylibre.com, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 6/9] arm64: dts: meson: g12a: Add UART A, B & C nodes and pins References: <20190307151342.7381-1-narmstrong@baylibre.com> <20190307151342.7381-7-narmstrong@baylibre.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 15/03/2019 22:24, Martin Blumenstingl a écrit : > Hi Neil, > > On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong wrote: >> >> This patch adds the 2 UART nodes in the EE power domain with the corresponding >> pinctrl nodes. > there are 3 UART controllers in the EE power domain Good catch ! > >> Signed-off-by: Neil Armstrong >> --- >> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 82 +++++++++++++++++++++ >> 1 file changed, 82 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> index 2a700bb45d04..50e2cd36e08b 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> @@ -113,6 +113,61 @@ >> #gpio-cells = <2>; >> gpio-ranges = <&periphs_pinctrl 0 0 86>; >> }; >> + >> + uart_a_pins: uart_a { > (this applies to all new nodes) > we started using dashes for the node names for new pin definitions on > the GX SoCs. > I don't remember where it was discussed exactly but I think this was > requested from Rob Yes I remember, will fix > > since G12A is a new SoC we should do it "right" from the beginning > > [...] >> + uart_ao_a_c_pins: uart_ao_a_c { >> + mux { >> + groups = "uart_ao_a_rx_c", >> + "uart_ao_a_tx_c"; >> + function = "uart_ao_a_c"; >> + bias-disable; >> + }; >> + }; > I'm fine with this part if you mention it in the subject and/or the description > uart_ao_a_c routes two pins from bank C (from the EE domain) to the > uart_AO controller (from the AO domain) Not sure DT is the right place for that, I think I'll remove this until we have it actually used somewhere. > >> + uart_b_pins: uart_b { >> + mux { >> + groups = "uart_b_tx", >> + "uart_b_rx"; >> + function = "uart_b"; >> + bias-disable; >> + }; >> + }; >> + >> + uart_c_pins: uart_c { >> + mux { >> + groups = "uart_c_tx", >> + "uart_c_rx"; >> + function = "uart_c"; >> + bias-disable; >> + }; >> + }; >> + >> + uart_c_cts_rts_pins: uart_c_cts_rts { >> + mux { >> + groups = "uart_c_cts", >> + "uart_c_rts"; >> + function = "uart_c"; >> + bias-disable; >> + }; >> + }; >> + }; >> }; >> >> hiu: bus@3c000 { >> @@ -256,6 +311,33 @@ >> compatible = "amlogic,meson-g12a-clk-measure"; >> reg = <0x0 0x18000 0x0 0x10>; >> }; >> + >> + uart_C: serial@22000 { >> + compatible = "amlogic,meson-gx-uart"; >> + reg = <0x0 0x22000 0x0 0x18>; >> + interrupts = ; >> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; > does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2 It seems so : https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L1020 Neil > > > Regards > Martin >