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From: Shiju Jose <shiju.jose@huawei.com>
To: Ira Weiny <ira.weiny@intel.com>,
	"dave.jiang@intel.com" <dave.jiang@intel.com>,
	"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
	Jonathan Cameron <jonathan.cameron@huawei.com>,
	"alison.schofield@intel.com" <alison.schofield@intel.com>,
	"nifan.cxl@gmail.com" <nifan.cxl@gmail.com>,
	"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
	"dave@stgolabs.net" <dave@stgolabs.net>,
	"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Linuxarm <linuxarm@huawei.com>,
	tanxiaofei <tanxiaofei@huawei.com>,
	"Zengtao (B)" <prime.zeng@hisilicon.com>
Subject: RE: [PATCH v5 4/6] cxl/events: Update DRAM Event Record to CXL spec rev 3.1
Date: Sat, 11 Jan 2025 09:16:07 +0000	[thread overview]
Message-ID: <5a0d7679f7d44f07a47eb47651f9b8ca@huawei.com> (raw)
In-Reply-To: <678166907eb67_17789429416@iweiny-mobl.notmuch>



>-----Original Message-----
>From: Ira Weiny <ira.weiny@intel.com>
>Sent: 10 January 2025 18:27
>To: Shiju Jose <shiju.jose@huawei.com>; dave.jiang@intel.com;
>dan.j.williams@intel.com; Jonathan Cameron
><jonathan.cameron@huawei.com>; alison.schofield@intel.com;
>nifan.cxl@gmail.com; vishal.l.verma@intel.com; ira.weiny@intel.com;
>dave@stgolabs.net; linux-cxl@vger.kernel.org
>Cc: linux-kernel@vger.kernel.org; Linuxarm <linuxarm@huawei.com>;
>tanxiaofei <tanxiaofei@huawei.com>; Zengtao (B) <prime.zeng@hisilicon.com>;
>Shiju Jose <shiju.jose@huawei.com>
>Subject: Re: [PATCH v5 4/6] cxl/events: Update DRAM Event Record to CXL spec
>rev 3.1
>
>shiju.jose@ wrote:
>> From: Shiju Jose <shiju.jose@huawei.com>
>>
>
>[snip]
>
>>
>>  TRACE_EVENT(cxl_dram,
>> @@ -527,6 +539,7 @@ TRACE_EVENT(cxl_dram,
>>  		__field(u64, dpa)
>>  		__field(u8, descriptor)
>>  		__field(u8, type)
>> +		__field(u8, sub_type)
>
>I just noticed this with the previous patch too.  To pack the record this should be
>below...

Hi Ira,

Thanks for reviewing and for the feedbacks. 
I have modified for your suggestions and will be in the v6.

Thanks,
Shiju

>
>>  		__field(u8, transaction_type)
>>  		__field(u8, channel)
>>  		__field(u16, validity_flags)
>> @@ -541,6 +554,10 @@ TRACE_EVENT(cxl_dram,
>>  		__field(u8, bank)	/* Out of order to pack trace record */
>>  		__field(u8, dpa_flags)	/* Out of order to pack trace record */
>
>Here.
>
>>  		__string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
>> +		__array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
>> +		__field(u8, sub_channel)
>> +		__field(u8, cme_threshold_ev_flags)
>> +		__field(u32, cvme_count)
>>  	),
>
>And these reordered too.  Like this:
>
>diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index
>cbaf6244d77f..6f4bf4925cbf 100644
>--- a/drivers/cxl/core/trace.h
>+++ b/drivers/cxl/core/trace.h
>@@ -539,7 +539,6 @@ TRACE_EVENT(cxl_dram,
>                __field(u64, dpa)
>                __field(u8, descriptor)
>                __field(u8, type)
>-               __field(u8, sub_type)
>                __field(u8, transaction_type)
>                __field(u8, channel)
>                __field(u16, validity_flags) @@ -553,11 +552,13 @@
>TRACE_EVENT(cxl_dram,
>                __field(u8, bank_group) /* Out of order to pack trace record */
>                __field(u8, bank)       /* Out of order to pack trace record */
>                __field(u8, dpa_flags)  /* Out of order to pack trace record */
>-               __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
>+               /* The following are out of order to pack the trace
>+ record */
>                __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE)
>+               __field(u32, cvme_count)
>+               __field(u8, sub_type)
>                __field(u8, sub_channel)
>                __field(u8, cme_threshold_ev_flags)
>-               __field(u32, cvme_count)
>+               __string(region_name, cxlr ? dev_name(&cxlr->dev) : "")
>        ),
>
>        TP_fast_assign(
>
>
>
>Other than that it looks good.  Perhaps Dave can just squash this hunk?
>
>Ira
>
>[snip]


  reply	other threads:[~2025-01-11  9:16 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-10 11:55 [PATCH v5 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
2025-01-10 11:55 ` [PATCH v5 1/6] cxl/events: Update Common Event Record " shiju.jose
2025-01-10 17:35   ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 2/6] cxl/events: Add Component Identifier formatting for " shiju.jose
2025-01-10 17:43   ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 3/6] cxl/events: Update General Media Event Record to " shiju.jose
2025-01-10 17:54   ` Ira Weiny
2025-01-10 18:30   ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 4/6] cxl/events: Update DRAM " shiju.jose
2025-01-10 18:27   ` Ira Weiny
2025-01-11  9:16     ` Shiju Jose [this message]
2025-01-10 11:55 ` [PATCH v5 5/6] cxl/events: Update Memory Module " shiju.jose
2025-01-10 18:46   ` Ira Weiny
2025-01-10 11:55 ` [PATCH v5 6/6] cxl/test: Update test code for event records " shiju.jose
2025-01-10 18:48   ` Ira Weiny
2025-01-10 16:06 ` [PATCH v5 0/6] Update Event Records " Jonathan Cameron
2025-01-10 16:46   ` Shiju Jose
2025-01-10 20:18     ` Dave Jiang
2025-01-11  9:22       ` Shiju Jose

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