From: Wadim Egorov <w.egorov@phytec.de>
To: Beleswar Padhi <b-padhi@ti.com>,
nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org
Cc: afd@ti.com, u-kumar1@ti.com, hnagalla@ti.com, jm@ti.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 32/33] arm64: dts: ti: k3-am64-ti-ipc-firmware: Refactor IPC cfg into new dtsi
Date: Thu, 28 Aug 2025 14:52:26 +0300 [thread overview]
Message-ID: <5a47c816-c39d-4dff-9028-2937ed7f9c9a@phytec.de> (raw)
In-Reply-To: <20250823160901.2177841-33-b-padhi@ti.com>
On 8/23/25 7:09 PM, Beleswar Padhi wrote:
> The TI K3 AM64 SoCs have multiple programmable remote processors like
> R5F, M4F etc. The TI SDKs for AM64 SoCs offer sample firmwares which
> could be run on these cores to demonstrate an "echo" IPC test. Those
> firmware require certain memory carveouts to be reserved from system
> memory, timers to be reserved, and certain mailbox configurations for
> interrupt based messaging. These configurations could be different for a
> different firmware.
>
> While DT is not meant for system configurations, at least refactor these
> configurations from board level DTS into a dtsi for now. This dtsi for
> TI IPC firmware is board-independent and can be applied to all boards
> from the same SoC Family. This gets rid of code duplication and allows
> more freedom for users developing custom firmware (or no firmware) to
> utilize system resources better; easily by swapping out this dtsi. To
> maintain backward compatibility, the dtsi is included in all boards.
>
> Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de> # phycore-am64x
Tested-by: Wadim Egorov <w.egorov@phytec.de> # phycore-am64x
> ---
> v2: Changelog:
> 1. Re-ordered patch from [PATCH 30/33] to [PATCH v2 32/33].
>
> Link to v1:
> https://lore.kernel.org/all/20250814223839.3256046-31-b-padhi@ti.com/
>
> .../boot/dts/ti/k3-am64-phycore-som.dtsi | 160 +----------------
> .../boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi | 162 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 156 +----------------
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 156 +----------------
> arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 156 +----------------
> .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 156 +----------------
> 6 files changed, 172 insertions(+), 774 deletions(-)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> index 1efd547b2ba6..af0fed6124e2 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> @@ -52,60 +52,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
> reg = <0x00 0xa0100000 0x00 0xf00000>;
> no-map;
> };
> -
> - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - mcu_m4fss_memory_region: m4f-memory@a4100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - rtos_ipc_memory_region: ipc-memories@a5000000 {
> - reg = <0x00 0xa5000000 0x00 0x00800000>;
> - alignment = <0x1000>;
> - no-map;
> - };
> };
>
> leds {
> @@ -238,67 +184,6 @@ &cpsw_port1 {
> status = "okay";
> };
>
> -&mailbox0_cluster2 {
> - status = "okay";
> -
> - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster4 {
> - status = "okay";
> -
> - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster6 {
> - status = "okay";
> -
> - mbox_m4_0: mbox-m4-0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -};
> -
> -/* main_timer8 is used by r5f0-0 */
> -&main_timer8 {
> - status = "reserved";
> -};
> -
> -/* main_timer9 is used by r5f0-1 */
> -&main_timer9 {
> - status = "reserved";
> -};
> -
> -/* main_timer10 is used by r5f1-0 */
> -&main_timer10 {
> - status = "reserved";
> -};
> -
> -/* main_timer11 is used by r5f1-1 */
> -&main_timer11 {
> - status = "reserved";
> -};
> -
> -&main_r5fss0 {
> - status = "okay";
> -};
> -
> &main_i2c0 {
> pinctrl-names = "default";
> pinctrl-0 = <&main_i2c0_pins_default>;
> @@ -373,49 +258,6 @@ &main_pktdma {
> bootph-all;
> };
>
> -&main_r5fss0 {
> - status = "okay";
> -};
> -
> -&main_r5fss0_core0 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
> - memory-region = <&main_r5fss0_core0_dma_memory_region>,
> - <&main_r5fss0_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss0_core1 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
> - memory-region = <&main_r5fss0_core1_dma_memory_region>,
> - <&main_r5fss0_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1 {
> - status = "okay";
> -};
> -
> -&main_r5fss1_core0 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
> - memory-region = <&main_r5fss1_core0_dma_memory_region>,
> - <&main_r5fss1_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1_core1 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
> - memory-region = <&main_r5fss1_core1_dma_memory_region>,
> - <&main_r5fss1_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&mcu_m4fss {
> - mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
> - memory-region = <&mcu_m4fss_dma_memory_region>,
> - <&mcu_m4fss_memory_region>;
> - status = "okay";
> -};
> -
> &ospi0 {
> pinctrl-names = "default";
> pinctrl-0 = <&ospi0_pins_default>;
> @@ -451,3 +293,5 @@ adc {
> ti,adc-channels = <0 1 2 3 4 5 6 7>;
> };
> };
> +
> +#include "k3-am64-ti-ipc-firmware.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi
> new file mode 100644
> index 000000000000..847495f76831
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi
> @@ -0,0 +1,162 @@
> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
> +/**
> + * Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs
> + *
> + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&reserved_memory {
> + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa1000000 0x00 0x100000>;
> + no-map;
> + };
> +
> + main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa1100000 0x00 0xf00000>;
> + no-map;
> + };
> +
> + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa2000000 0x00 0x100000>;
> + no-map;
> + };
> +
> + main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa2100000 0x00 0xf00000>;
> + no-map;
> + };
> +
> + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa3000000 0x00 0x100000>;
> + no-map;
> + };
> +
> + main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa3100000 0x00 0xf00000>;
> + no-map;
> + };
> +
> + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa4000000 0x00 0x100000>;
> + no-map;
> + };
> +
> + mcu_m4fss_memory_region: m4f-memory@a4100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0xa4100000 0x00 0xf00000>;
> + no-map;
> + };
> +
> + rtos_ipc_memory_region: ipc-memories@a5000000 {
> + reg = <0x00 0xa5000000 0x00 0x00800000>;
> + alignment = <0x1000>;
> + no-map;
> + };
> +};
> +
> +&mailbox0_cluster2 {
> + status = "okay";
> +
> + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
> + ti,mbox-rx = <0 0 2>;
> + ti,mbox-tx = <1 0 2>;
> + };
> +
> + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
> + ti,mbox-rx = <2 0 2>;
> + ti,mbox-tx = <3 0 2>;
> + };
> +};
> +
> +&mailbox0_cluster4 {
> + status = "okay";
> +
> + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
> + ti,mbox-rx = <0 0 2>;
> + ti,mbox-tx = <1 0 2>;
> + };
> +
> + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
> + ti,mbox-rx = <2 0 2>;
> + ti,mbox-tx = <3 0 2>;
> + };
> +};
> +
> +&mailbox0_cluster6 {
> + status = "okay";
> +
> + mbox_m4_0: mbox-m4-0 {
> + ti,mbox-rx = <0 0 2>;
> + ti,mbox-tx = <1 0 2>;
> + };
> +};
> +
> +/* main_timer8 is used by r5f0-0 */
> +&main_timer8 {
> + status = "reserved";
> +};
> +
> +/* main_timer9 is used by r5f0-1 */
> +&main_timer9 {
> + status = "reserved";
> +};
> +
> +/* main_timer10 is used by r5f1-0 */
> +&main_timer10 {
> + status = "reserved";
> +};
> +
> +/* main_timer11 is used by r5f1-1 */
> +&main_timer11 {
> + status = "reserved";
> +};
> +
> +&main_r5fss0 {
> + status = "okay";
> +};
> +
> +&main_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
> + memory-region = <&main_r5fss0_core0_dma_memory_region>,
> + <&main_r5fss0_core0_memory_region>;
> + status = "okay";
> +};
> +
> +&main_r5fss0_core1 {
> + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
> + memory-region = <&main_r5fss0_core1_dma_memory_region>,
> + <&main_r5fss0_core1_memory_region>;
> + status = "okay";
> +};
> +
> +&main_r5fss1 {
> + status = "okay";
> +};
> +
> +&main_r5fss1_core0 {
> + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
> + memory-region = <&main_r5fss1_core0_dma_memory_region>,
> + <&main_r5fss1_core0_memory_region>;
> + status = "okay";
> +};
> +
> +&main_r5fss1_core1 {
> + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
> + memory-region = <&main_r5fss1_core1_dma_memory_region>,
> + <&main_r5fss1_core1_memory_region>;
> + status = "okay";
> +};
> +
> +&mcu_m4fss {
> + mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
> + memory-region = <&mcu_m4fss_dma_memory_region>,
> + <&mcu_m4fss_memory_region>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 7640c5efe9b8..05b7cdd25a8c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -64,60 +64,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
> reg = <0x00 0xa0100000 0x00 0xf00000>;
> no-map;
> };
> -
> - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - mcu_m4fss_memory_region: m4f-memory@a4100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - rtos_ipc_memory_region: ipc-memories@a5000000 {
> - reg = <0x00 0xa5000000 0x00 0x00800000>;
> - alignment = <0x1000>;
> - no-map;
> - };
> };
>
> evm_12v0: regulator-0 {
> @@ -727,106 +673,6 @@ partition@3fc0000 {
> };
> };
>
> -&mailbox0_cluster2 {
> - status = "okay";
> -
> - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster4 {
> - status = "okay";
> -
> - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster6 {
> - status = "okay";
> -
> - mbox_m4_0: mbox-m4-0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -};
> -
> -&main_r5fss0 {
> - status = "okay";
> -};
> -
> -&main_r5fss0_core0 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
> - memory-region = <&main_r5fss0_core0_dma_memory_region>,
> - <&main_r5fss0_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss0_core1 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
> - memory-region = <&main_r5fss0_core1_dma_memory_region>,
> - <&main_r5fss0_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1 {
> - status = "okay";
> -};
> -
> -&main_r5fss1_core0 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
> - memory-region = <&main_r5fss1_core0_dma_memory_region>,
> - <&main_r5fss1_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1_core1 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
> - memory-region = <&main_r5fss1_core1_dma_memory_region>,
> - <&main_r5fss1_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&mcu_m4fss {
> - mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
> - memory-region = <&mcu_m4fss_dma_memory_region>,
> - <&mcu_m4fss_memory_region>;
> - status = "okay";
> -};
> -
> -/* main_timer8 is used by r5f0-0 */
> -&main_timer8 {
> - status = "reserved";
> -};
> -
> -/* main_timer9 is used by r5f0-1 */
> -&main_timer9 {
> - status = "reserved";
> -};
> -
> -/* main_timer10 is used by r5f1-0 */
> -&main_timer10 {
> - status = "reserved";
> -};
> -
> -/* main_timer11 is used by r5f1-1 */
> -&main_timer11 {
> - status = "reserved";
> -};
> -
> &serdes_ln_ctrl {
> idle-states = <AM64_SERDES0_LANE0_PCIE0>;
> };
> @@ -890,3 +736,5 @@ &icssg1_iep0 {
> pinctrl-names = "default";
> pinctrl-0 = <&icssg1_iep0_pins_default>;
> };
> +
> +#include "k3-am64-ti-ipc-firmware.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index fb8bd66f2f94..cc1569a6519b 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -62,60 +62,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
> reg = <0x00 0xa0100000 0x00 0xf00000>;
> no-map;
> };
> -
> - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - mcu_m4fss_memory_region: m4f-memory@a4100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - rtos_ipc_memory_region: ipc-memories@a5000000 {
> - reg = <0x00 0xa5000000 0x00 0x00800000>;
> - alignment = <0x1000>;
> - no-map;
> - };
> };
>
> vusb_main: regulator-0 {
> @@ -642,106 +588,6 @@ partition@3fc0000 {
> };
> };
>
> -&mailbox0_cluster2 {
> - status = "okay";
> -
> - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster4 {
> - status = "okay";
> -
> - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster6 {
> - status = "okay";
> -
> - mbox_m4_0: mbox-m4-0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -};
> -
> -&main_r5fss0 {
> - status = "okay";
> -};
> -
> -&main_r5fss0_core0 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
> - memory-region = <&main_r5fss0_core0_dma_memory_region>,
> - <&main_r5fss0_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss0_core1 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
> - memory-region = <&main_r5fss0_core1_dma_memory_region>,
> - <&main_r5fss0_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1 {
> - status = "okay";
> -};
> -
> -&main_r5fss1_core0 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
> - memory-region = <&main_r5fss1_core0_dma_memory_region>,
> - <&main_r5fss1_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1_core1 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
> - memory-region = <&main_r5fss1_core1_dma_memory_region>,
> - <&main_r5fss1_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&mcu_m4fss {
> - mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
> - memory-region = <&mcu_m4fss_dma_memory_region>,
> - <&mcu_m4fss_memory_region>;
> - status = "okay";
> -};
> -
> -/* main_timer8 is used by r5f0-0 */
> -&main_timer8 {
> - status = "reserved";
> -};
> -
> -/* main_timer9 is used by r5f0-1 */
> -&main_timer9 {
> - status = "reserved";
> -};
> -
> -/* main_timer10 is used by r5f1-0 */
> -&main_timer10 {
> - status = "reserved";
> -};
> -
> -/* main_timer11 is used by r5f1-1 */
> -&main_timer11 {
> - status = "reserved";
> -};
> -
> &ecap0 {
> status = "okay";
> /* PWM is available on Pin 1 of header J3 */
> @@ -755,3 +601,5 @@ &eqep0 {
> pinctrl-names = "default";
> pinctrl-0 = <&main_eqep0_pins_default>;
> };
> +
> +#include "k3-am64-ti-ipc-firmware.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> index 8cb61f831734..ce23362b88c3 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> @@ -126,60 +126,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
> reg = <0x00 0xa0100000 0x00 0xf00000>;
> no-map;
> };
> -
> - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - mcu_m4fss_memory_region: m4f-memory@a4100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - rtos_ipc_memory_region: ipc-memories@a5000000 {
> - reg = <0x00 0xa5000000 0x00 0x00800000>;
> - alignment = <0x1000>;
> - no-map;
> - };
> };
>
> vdd_mmc0: regulator-vdd-mmc0 {
> @@ -281,63 +227,6 @@ ethernet_phy2: ethernet-phy@f {
> };
> };
>
> -&mailbox0_cluster2 {
> - status = "okay";
> -
> - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster4 {
> - status = "okay";
> -
> - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster6 {
> - status = "okay";
> -
> - mbox_m4_0: mbox-m4-0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -};
> -
> -/* main_timer8 is used by r5f0-0 */
> -&main_timer8 {
> - status = "reserved";
> -};
> -
> -/* main_timer9 is used by r5f0-1 */
> -&main_timer9 {
> - status = "reserved";
> -};
> -
> -/* main_timer10 is used by r5f1-0 */
> -&main_timer10 {
> - status = "reserved";
> -};
> -
> -/* main_timer11 is used by r5f1-1 */
> -&main_timer11 {
> - status = "reserved";
> -};
> -
> &main_i2c0 {
> pinctrl-names = "default";
> pinctrl-0 = <&main_i2c0_default_pins>;
> @@ -535,49 +424,6 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */
> };
> };
>
> -&main_r5fss0 {
> - status = "okay";
> -};
> -
> -&main_r5fss0_core0 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
> - memory-region = <&main_r5fss0_core0_dma_memory_region>,
> - <&main_r5fss0_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss0_core1 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
> - memory-region = <&main_r5fss0_core1_dma_memory_region>,
> - <&main_r5fss0_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1 {
> - status = "okay";
> -};
> -
> -&main_r5fss1_core0 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
> - memory-region = <&main_r5fss1_core0_dma_memory_region>,
> - <&main_r5fss1_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1_core1 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
> - memory-region = <&main_r5fss1_core1_dma_memory_region>,
> - <&main_r5fss1_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&mcu_m4fss {
> - mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
> - memory-region = <&mcu_m4fss_dma_memory_region>,
> - <&mcu_m4fss_memory_region>;
> - status = "okay";
> -};
> -
> /* SoC default UART console */
> &main_uart0 {
> pinctrl-names = "default";
> @@ -656,3 +502,5 @@ &usbss0 {
> ti,vbus-divider;
> ti,usb2-only;
> };
> +
> +#include "k3-am64-ti-ipc-firmware.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
> index 860b79aa5ef5..e752fc8b0a88 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
> @@ -42,60 +42,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
> reg = <0x00 0xa0100000 0x00 0xf00000>;
> no-map;
> };
> -
> - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa1100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa2100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa3100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4000000 0x00 0x100000>;
> - no-map;
> - };
> -
> - mcu_m4fss_memory_region: m4f-memory@a4100000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0xa4100000 0x00 0xf00000>;
> - no-map;
> - };
> -
> - rtos_ipc_memory_region: ipc-memories@a5000000 {
> - reg = <0x00 0xa5000000 0x00 0x00800000>;
> - alignment = <0x1000>;
> - no-map;
> - };
> };
>
> reg_1v8: regulator-1v8 {
> @@ -142,106 +88,6 @@ eeprom1: eeprom@54 {
> };
> };
>
> -&mailbox0_cluster2 {
> - status = "okay";
> -
> - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster4 {
> - status = "okay";
> -
> - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -
> - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
> - ti,mbox-rx = <2 0 2>;
> - ti,mbox-tx = <3 0 2>;
> - };
> -};
> -
> -&mailbox0_cluster6 {
> - status = "okay";
> -
> - mbox_m4_0: mbox-m4-0 {
> - ti,mbox-rx = <0 0 2>;
> - ti,mbox-tx = <1 0 2>;
> - };
> -};
> -
> -/* main_timer8 is used by r5f0-0 */
> -&main_timer8 {
> - status = "reserved";
> -};
> -
> -/* main_timer9 is used by r5f0-1 */
> -&main_timer9 {
> - status = "reserved";
> -};
> -
> -/* main_timer10 is used by r5f1-0 */
> -&main_timer10 {
> - status = "reserved";
> -};
> -
> -/* main_timer11 is used by r5f1-1 */
> -&main_timer11 {
> - status = "reserved";
> -};
> -
> -&main_r5fss0 {
> - status = "okay";
> -};
> -
> -&main_r5fss0_core0 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
> - memory-region = <&main_r5fss0_core0_dma_memory_region>,
> - <&main_r5fss0_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss0_core1 {
> - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
> - memory-region = <&main_r5fss0_core1_dma_memory_region>,
> - <&main_r5fss0_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1 {
> - status = "okay";
> -};
> -
> -&main_r5fss1_core0 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
> - memory-region = <&main_r5fss1_core0_dma_memory_region>,
> - <&main_r5fss1_core0_memory_region>;
> - status = "okay";
> -};
> -
> -&main_r5fss1_core1 {
> - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
> - memory-region = <&main_r5fss1_core1_dma_memory_region>,
> - <&main_r5fss1_core1_memory_region>;
> - status = "okay";
> -};
> -
> -&mcu_m4fss {
> - mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
> - memory-region = <&mcu_m4fss_dma_memory_region>,
> - <&mcu_m4fss_memory_region>;
> - status = "okay";
> -};
> -
> &ospi0 {
> status = "okay";
> pinctrl-names = "default";
> @@ -315,3 +161,5 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0)
> >;
> };
> };
> +
> +#include "k3-am64-ti-ipc-firmware.dtsi"
next prev parent reply other threads:[~2025-08-28 11:52 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-23 16:08 [PATCH v2 00/33] Refactor TI IPC DT configs into dtsi Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 01/33] arm64: dts: ti: k3-j7200: Enable remote processors at board level Beleswar Padhi
2025-08-25 14:18 ` Andrew Davis
2025-08-23 16:08 ` [PATCH v2 02/33] arm64: dts: ti: k3-j721e: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 03/33] arm64: dts: ti: k3-j721s2: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 04/33] arm64: dts: ti: k3-j784s4-j742s2: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 05/33] arm64: dts: ti: k3-am62p-j722s: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 06/33] arm64: dts: ti: k3-am62: " Beleswar Padhi
2025-08-28 11:43 ` Wadim Egorov
2025-08-23 16:08 ` [PATCH v2 07/33] arm64: dts: ti: k3-am62a: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 08/33] arm64: dts: ti: k3-am64: " Beleswar Padhi
2025-08-28 11:46 ` Wadim Egorov
2025-08-23 16:08 ` [PATCH v2 09/33] arm64: dts: ti: k3-am65: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 10/33] arm64: dts: ti: k3-am62: Enable Mailbox nodes at the " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 11/33] arm64: dts: ti: k3-am62a: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 12/33] arm64: dts: ti: k3-am6*-boards: Add label to reserved-memory node Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 13/33] arm64: dts: ti: k3-j721e-beagleboneai64: Add missing cfg for TI IPC FW Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 14/33] arm64: dts: ti: k3-am62p-verdin: Add missing cfg for TI IPC Firmware Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 15/33] arm64: dts: ti: k3-am62-verdin: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 16/33] arm64: dts: ti: k3-am62-pocketbeagle2: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 17/33] arm64: dts: ti: k3-am642-sr-som: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 18/33] arm64: dts: ti: k3-am64-phycore-som: " Beleswar Padhi
2025-08-28 11:42 ` Wadim Egorov
2025-08-29 6:02 ` Beleswar Prasad Padhi
2025-08-23 16:08 ` [PATCH v2 19/33] arm64: dts: ti: k3-am642-tqma64xxl: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 20/33] Revert "arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveout locations" Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 21/33] Revert "arm64: dts: ti: k3-j721e-beagleboneai64: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 22/33] arm64: dts: ti: k3-j721e-beagleboneai64: Switch MAIN R5F clusters to Split-mode Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 23/33] arm64: dts: ti: k3-j7200-ti-ipc-firmware: Refactor IPC cfg into new dtsi Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 24/33] arm64: dts: ti: k3-j721e-ti-ipc-firmware: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 25/33] arm64: dts: ti: k3-j721s2-ti-ipc-firmware: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 26/33] arm64: dts: ti: k3-j784s4-j742s2-ti-ipc-firmware-common: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 27/33] arm64: dts: ti: k3-j784s4-ti-ipc-firmware: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 28/33] arm64: dts: ti: k3-j722s-ti-ipc-firmware: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 29/33] arm64: dts: ti: k3-am62p-ti-ipc-firmware: " Beleswar Padhi
2025-08-23 16:08 ` [PATCH v2 30/33] arm64: dts: ti: k3-am62-ti-ipc-firmware: " Beleswar Padhi
2025-08-28 11:51 ` Wadim Egorov
2025-08-23 16:08 ` [PATCH v2 31/33] arm64: dts: ti: k3-am62a-ti-ipc-firmware: " Beleswar Padhi
2025-08-23 16:09 ` [PATCH v2 32/33] arm64: dts: ti: k3-am64-ti-ipc-firmware: " Beleswar Padhi
2025-08-28 11:52 ` Wadim Egorov [this message]
2025-08-23 16:09 ` [PATCH v2 33/33] arm64: dts: ti: k3-am65-ti-ipc-firmware: " Beleswar Padhi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5a47c816-c39d-4dff-9028-2937ed7f9c9a@phytec.de \
--to=w.egorov@phytec.de \
--cc=afd@ti.com \
--cc=b-padhi@ti.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=hnagalla@ti.com \
--cc=jm@ti.com \
--cc=kristo@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=nm@ti.com \
--cc=robh@kernel.org \
--cc=u-kumar1@ti.com \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).