Re: [PATCH V5 08/12] perf/x86/intel: Add Icelake support

Peter Zijlstra
2019-04-11T09:01:04Z

On Wed, Apr 10, 2019 at 09:47:20PM +0200, Peter Zijlstra wrote:
> Sure, those are actually forced 0 with the existing thing.
>
> I'll go fold smething like back in. Thanks!

> > @@ -3472,7 +3475,7 @@ icl_get_event_constraints(struct cpu_hw_events *cpuc,
> > int idx,
> > * Force instruction:ppp in Fixed counter 0
> > */
> > if ((event->attr.precise_ip == 3) &&
> > - (event->hw.config == X86_CONFIG(.event=0xc0)))
> > + (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)))
> > return &fixed_counter0_constraint;
> >
> > return hsw_get_event_constraints(cpuc, idx, event);

Staring at that I came up with the below; how does that look?

Note: FIXED_EVENT_CONSTRAINT(0x00c0, 0) has FIXED_EVENT_FLAGS for
->cmask and includes the correct event code.

---
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3433,7 +3433,7 @@ icl_get_event_constraints(struct cpu_hw_
* Force instruction:ppp in Fixed counter 0
*/
if ((event->attr.precise_ip == 3) &&
- (event->hw.config == X86_CONFIG(.event=0xc0)))
+ constraint_match(&fixed_counter0_constraint, event->hw.config))
return &fixed_counter0_constraint;

return hsw_get_event_constraints(cpuc, idx, event);