Re: [PATCH V5 05/12] perf/x86/intel: Support adaptive PEBSv4

Peter Zijlstra
2019-04-08T14:55:18Z

On Tue, Apr 02, 2019 at 12:45:02PM -0700, kan.liang@linux.intel.com wrote:
> +static u64 pebs_update_adaptive_cfg(struct perf_event *event)
> +{
> + struct perf_event_attr *attr = &event->attr;
> + u64 sample_type = attr->sample_type;
> + u64 pebs_data_cfg = 0;
> + bool gprs, tsx_weight;
> +
> + if ((sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) ||
> + attr->precise_ip < 2) {
> +
> + if (sample_type & PERF_PEBS_MEMINFO_TYPE)
> + pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
> +
> + /*
> + * Cases we need the registers:
> + * + user requested registers
> + * + precise_ip < 2 for the non event IP
> + * + For RTM TSX weight we need GPRs too for the abort
> + * code. But we don't want to force GPRs for all other
> + * weights. So add it only collectfor the RTM abort event.
> + */
> + gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
> + (attr->sample_regs_intr & 0xffffffff);

did that want to be:

(attr->sample_regs_intr & PEBS_GPRS_REGS);
?

> + tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT) &&
> + ((attr->config & 0xffff) == x86_pmu.force_gpr_event);

Why does that force_gpr_event exist? and why isn't it called
rtm_abort_event?

Also did that want to be:

(attr->config & INTEL_ARCH_EVENT_MASK)
?

> + if (gprs || (attr->precise_ip < 2) || tsx_weight)
> + pebs_data_cfg |= PEBS_DATACFG_GPRS;
> +
> + if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
> + (attr->sample_regs_intr >> 32))

Surely, you meant:

(attr->sample_regs_intr & PEBS_XMM_REGS)
?

> + pebs_data_cfg |= PEBS_DATACFG_XMMS;
> +
> + if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
> + /*
> + * For now always log all LBRs. Could configure this
> + * later.
> + */
> + pebs_data_cfg |= PEBS_DATACFG_LBRS |
> + ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
> + }
> + }
> + return pebs_data_cfg;
> +}